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Fixes A7-relative JSRs.

I completely withdraw my earlier statement re: the test cases.
This commit is contained in:
Thomas Harte 2020-01-04 22:22:33 -05:00
parent 42a9585321
commit a28c52c250
4 changed files with 10 additions and 9 deletions

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@ -68,8 +68,8 @@
</TestAction> </TestAction>
<LaunchAction <LaunchAction
buildConfiguration = "Release" buildConfiguration = "Release"
selectedDebuggerIdentifier = "Xcode.DebuggerFoundation.Debugger.LLDB" selectedDebuggerIdentifier = ""
selectedLauncherIdentifier = "Xcode.DebuggerFoundation.Launcher.LLDB" selectedLauncherIdentifier = "Xcode.IDEFoundation.Launcher.PosixSpawn"
enableASanStackUseAfterReturn = "YES" enableASanStackUseAfterReturn = "YES"
disableMainThreadChecker = "YES" disableMainThreadChecker = "YES"
launchStyle = "0" launchStyle = "0"

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@ -32,9 +32,6 @@ So the output is very scattergun approach, with a lot of redundancy.
## Questionable Results ## Questionable Results
I am presently unconvinced by the results for: I am presently unconvinced by the results for the N flag on many of the [A/S/N]BCD results, as these often seem to conflict with Bart Trzynadlowski's 68knotes.txt.
* the N flag on many of the [A/S/N]BCD results, as these often seem to conflict with Bart Trzynadlowski's 68knotes.txt; and
* the alleged results of A7-relative JSR, for which the emulator I was testing against appears to have computed a target address for the value of A7 after pushing the existing PC to the stack, which is unlikely because the first of that instruction's program fetches occurs before any stack activity.
This emulator seems not yet to generate values for the undocumented flags of DIVU and DIVS that match those listed here, but that's through lack of documentation. The objective here is to test my implementation of behaviour I am able to find descriptions of against other people's implementations of that same behaviour, to flush out errors in my comprehension and implementation. This emulator seems not yet to generate values for the undocumented flags of DIVU and DIVS that match those listed here, but that's through lack of documentation. The objective here is to test my implementation of behaviour I am able to find descriptions of against other people's implementations of that same behaviour, to flush out errors in my comprehension and implementation.

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@ -27,7 +27,7 @@
- (void)setUp { - (void)setUp {
// To limit tests run to a subset of files and/or of tests, uncomment and fill in below. // To limit tests run to a subset of files and/or of tests, uncomment and fill in below.
// _fileSet = [NSSet setWithArray:@[@"move_tofrom_srccr.json"]]; // _fileSet = [NSSet setWithArray:@[@"jmp_jsr.json"]];
// _testSet = [NSSet setWithArray:@[@"CHK 41a8"]]; // _testSet = [NSSet setWithArray:@[@"CHK 41a8"]];
} }

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@ -2371,6 +2371,10 @@ struct ProcessorStorageConstructor {
// ... but otherwise assume that the true source of a destination will be the computed source address. // ... but otherwise assume that the true source of a destination will be the computed source address.
program.set_source(storage_, &storage_.effective_address_[0]); program.set_source(storage_, &storage_.effective_address_[0]);
// Beware below: PrepareJSR will pre-emptively subtract four from A7 in order
// to facilitate the peculiar stack write order of JSR. Therefore any address
// calculation that might be a function of A7 needs to be done before PrepareJSR.
const int mode = combined_mode(ea_mode, ea_register); const int mode = combined_mode(ea_mode, ea_register);
switch(mode) { switch(mode) {
default: continue; default: continue;
@ -2391,15 +2395,15 @@ struct ProcessorStorageConstructor {
case XXXw: // JSR (xxx).W case XXXw: // JSR (xxx).W
case d16PC: // JSR (d16, PC) case d16PC: // JSR (d16, PC)
case d16An: // JSR (d16, An) case d16An: // JSR (d16, An)
op(Action::PrepareJSR);
op(address_action_for_mode(mode) | MicroOp::SourceMask); op(address_action_for_mode(mode) | MicroOp::SourceMask);
op(Action::PrepareJSR);
op(Action::PerformOperation, seq("n np nW+ nw np", { ea(1), ea(1) })); op(Action::PerformOperation, seq("n np nW+ nw np", { ea(1), ea(1) }));
break; break;
case d8PCXn: // JSR (d8, PC, Xn) case d8PCXn: // JSR (d8, PC, Xn)
case d8AnXn: // JSR (d8, An, Xn) case d8AnXn: // JSR (d8, An, Xn)
op(Action::PrepareJSR);
op(calc_action_for_mode(mode) | MicroOp::SourceMask); op(calc_action_for_mode(mode) | MicroOp::SourceMask);
op(Action::PrepareJSR);
op(Action::PerformOperation, seq("n nn np nW+ nw np", { ea(1), ea(1) })); op(Action::PerformOperation, seq("n nn np nW+ nw np", { ea(1), ea(1) }));
break; break;
} }