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Corrected CPx bit 3 and 5 flags. I think only BIT n, (HL) with the famous MEMPTR reliance is preventing a complete pass by Zexall now.

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Thomas Harte 2017-06-04 14:59:18 -04:00
parent f5c910beb7
commit a2f01b4a46
1 changed files with 3 additions and 1 deletions
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4
Processors/Z80/Z80.hpp
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@ -1205,8 +1205,10 @@ template <class T> class Processor {
parity_overflow_result_ = bc_.full ? Flag::Parity : 0; \
half_carry_result_ = halfResult; \
subtract_flag_ = Flag::Subtract; \
sign_result_ = zero_result_ = result; \
\
result -= (halfResult >> 4)&1; \
bit53_result_ = (uint8_t)((result&0x8) | ((result&0x2) << 4)); \
sign_result_ = zero_result_ = result;
case MicroOp::CPDR: {
CPxR_STEP(-1);