mirror of
https://github.com/TomHarte/CLK.git
synced 2026-04-25 11:17:26 +00:00
Makes some sort of first attempt at having the IWM read.
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@@ -59,8 +59,12 @@ uint8_t IWM::read(int address) {
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return 0xff;
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case ENABLE: /* Read data register. */
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if(data_register_ & 0x80) {
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printf("[%02x] ", data_register_);
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data_register_ = 0;
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}
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printf("Reading data register\n");
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return 0x00;
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return data_register_;
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case Q6: case Q6|ENABLE: {
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/*
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@@ -257,11 +261,49 @@ void IWM::run_for(const Cycles cycles) {
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}
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// Activity otherwise depends on mode and motor state.
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const bool run_disk = drive_motor_on_ && drives_[active_drive_];
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int integer_cycles = cycles.as_int();
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switch(state_ & (Q6 | Q7 | ENABLE)) {
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case ENABLE: // i.e. read mode.
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while(integer_cycles--) {
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if(run_disk) {
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drives_[active_drive_]->run_for(Cycles(1));
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}
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++cycles_since_shift_;
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if(cycles_since_shift_ == bit_length_ + Cycles(2)) {
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propose_shift(0);
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}
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}
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break;
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default:
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if(run_disk) drives_[active_drive_]->run_for(cycles);
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break;
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}
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}
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void IWM::process_event(const Storage::Disk::Track::Event &event) {
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switch(event.type) {
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case Storage::Disk::Track::Event::IndexHole: return;
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case Storage::Disk::Track::Event::FluxTransition:
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propose_shift(1);
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break;
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}
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}
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void IWM::propose_shift(uint8_t bit) {
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// TODO: synchronous mode.
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shift_register_ = uint8_t((shift_register_ << 1) | bit);
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if(shift_register_ & 0x80) {
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printf("%02x -> data\n", shift_register_);
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data_register_ = shift_register_;
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shift_register_ = 0;
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}
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cycles_since_shift_ = Cycles(0);
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}
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void IWM::set_drive(int slot, Storage::Disk::Drive *drive) {
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drives_[slot] = drive;
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drive->set_event_delegate(this);
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}
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@@ -16,7 +16,8 @@
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namespace Apple {
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class IWM {
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class IWM:
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public Storage::Disk::Drive::EventDelegate {
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public:
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IWM(int clock_rate);
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@@ -42,8 +43,12 @@ class IWM {
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void set_drive(int slot, Storage::Disk::Drive *drive);
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private:
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// Storage::Disk::Drive::EventDelegate.
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void process_event(const Storage::Disk::Track::Event &event) override;
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const int clock_rate_;
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uint8_t data_register_ = 0;
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uint8_t mode_ = 0;
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bool read_write_ready_ = true;
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bool write_overran_ = false;
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@@ -58,6 +63,9 @@ class IWM {
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void access(int address);
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uint8_t shift_register_ = 0;
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void propose_shift(uint8_t bit);
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Cycles cycles_since_shift_;
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Cycles bit_length_;
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};
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