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https://github.com/TomHarte/CLK.git
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Ties bitplane collection to line position.
Outgoing bug: incrementing the video relative offset too often, due to cycles that are discovered to be CPU-targetted.
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@ -222,7 +222,7 @@ void Chipset::flush_output() {
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pixels_ = nullptr;
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}
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/// @returns @c true if this was a CPU slot; @c false otherwise.
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template <int cycle, bool stop_if_cpu> bool Chipset::perform_cycle() {
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constexpr auto BlitterFlag = DMAMask<DMAFlag::Blitter, DMAFlag::AllBelow>::value;
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constexpr auto BitplaneFlag = DMAMask<DMAFlag::Bitplane, DMAFlag::AllBelow>::value;
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@ -239,7 +239,7 @@ template <int cycle, bool stop_if_cpu> bool Chipset::perform_cycle() {
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if((dma_control_ & BitplaneFlag) == BitplaneFlag) {
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// TODO: offer a cycle for bitplane collection.
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// Probably need to indicate odd or even?
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if(fetch_horizontal_ && fetch_vertical_ && bitplanes_.template advance<cycle&1>()) {
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if(fetch_horizontal_ && fetch_vertical_ && bitplanes_.advance(cycle)) { // TODO: cycle should be relative to start of collection.
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did_fetch_ = true;
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return false;
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}
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@ -278,6 +278,11 @@ template <int cycle, bool stop_if_cpu> bool Chipset::perform_cycle() {
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return (dma_control_ & BlitterFlag) != BlitterFlag || !blitter_.advance();
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}
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/// Performs all slots starting with @c first_slot and ending just before @c last_slot.
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/// If @c stop_on_cpu is true, stops upon discovery of a CPU slot.
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///
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/// @returns the number of slots completed if @c stop_on_cpu was true and a CPU slot was found.
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/// @c -1 otherwise.
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template <bool stop_on_cpu> int Chipset::advance_slots(int first_slot, int last_slot) {
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if(first_slot == last_slot) {
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return -1;
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@ -753,37 +758,32 @@ void Chipset::perform(const CPU::MC68000::Microcycle &cycle) {
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// MARK: - Bitplanes.
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template <bool is_odd> bool Chipset::Bitplanes::advance() {
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// Offset is preincremented in order to simplify the exit
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// pathways below. As a result all in-switch offsets are
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// off by 1. This is dealt with in the macro.
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++collection_offset_;
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bool Chipset::Bitplanes::advance(int cycle) {
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// TODO: possibly dispatch a BitplaneData.
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// The chipset has responsibility for applying a delay,
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// and the pixel-level start/stop boundaries.
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#define BIND_CYCLE(offset, plane) \
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case (offset + 1)&7: \
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if(plane_count_ > plane) { \
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#define BIND_CYCLE(offset, plane) \
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case offset: \
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if(plane_count_ > plane) { \
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next[plane] = ram_[pointer_[plane] & ram_mask_]; \
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++pointer_[plane]; \
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if constexpr (!plane) { \
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chipset_.post_bitplanes(next); \
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} \
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return true; \
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} \
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++pointer_[plane]; \
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if constexpr (!plane) { \
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chipset_.post_bitplanes(next); \
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} \
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return true; \
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} \
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return false;
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if(is_high_res_) {
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// TODO: I'm unclear whether this is correct, or merely
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// an artefact of the way the Hardware Reference Manual
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// depicts per-line DMA responsibilities.
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if(collection_offset_ < 4) {
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if(cycle < 4) {
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return false;
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}
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switch(collection_offset_&7) {
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switch(cycle&7) {
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default: return false;
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BIND_CYCLE(0, 3);
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BIND_CYCLE(1, 1);
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@ -795,7 +795,7 @@ template <bool is_odd> bool Chipset::Bitplanes::advance() {
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BIND_CYCLE(7, 0);
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}
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} else {
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switch(collection_offset_&7) {
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switch(cycle&7) {
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default: return false;
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BIND_CYCLE(1, 3);
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BIND_CYCLE(2, 5);
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@ -811,7 +811,6 @@ template <bool is_odd> bool Chipset::Bitplanes::advance() {
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void Chipset::Bitplanes::do_end_of_line() {
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// TODO: apply modulos.
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collection_offset_ = 0;
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}
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void Chipset::Bitplanes::set_control(uint16_t control) {
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@ -171,13 +171,12 @@ class Chipset {
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public:
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using DMADevice::DMADevice;
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template <bool is_odd> bool advance();
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bool advance(int cycle);
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void do_end_of_line();
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void set_control(uint16_t);
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private:
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bool is_high_res_ = false;
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int collection_offset_ = 0;
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int plane_count_ = 0;
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BitplaneData next;
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