From a5f0761a437875da6954db4b6afc9fb85a7a2dae Mon Sep 17 00:00:00 2001 From: Thomas Harte Date: Sun, 7 Jul 2019 14:13:00 -0400 Subject: [PATCH] Copies in notes for required test functions. --- .../Mac/Clock SignalTests/6522Tests.swift | 103 ++++++++++++++++++ 1 file changed, 103 insertions(+) diff --git a/OSBindings/Mac/Clock SignalTests/6522Tests.swift b/OSBindings/Mac/Clock SignalTests/6522Tests.swift index 9a5d412f6..83f2851ad 100644 --- a/OSBindings/Mac/Clock SignalTests/6522Tests.swift +++ b/OSBindings/Mac/Clock SignalTests/6522Tests.swift @@ -125,4 +125,107 @@ class MOS6522Tests: XCTestCase { XCTAssert($0.value(forRegister: 0) == 0x8a, "Data direction register should mix input and output; got \($0.value(forRegister: 0))") } } + + func testShiftDisabled() { + /* + Mode 0 disables the Shift Register. In this mode the microprocessor can + write or read the SR and the SR will shift on each CB1 positive edge + shifting in the value on CB2. In this mode the SR Interrupt Flag is + disabled (held to a logic 0). + */ + } + + func testShiftInUnderT2() { + /* + In mode 1, the shifting rate is controlled by the low order 8 bits of T2 + (Figure 22). Shift pulses are generated on the CB1 pin to control shifting + in external devices. The time between transitions of this output clock is a + function of the system clock period and the contents of the low order T2 + latch (N). + + The shifting operation is triggered by the read or write of the SR if the + SR flag is set in the IFR. Otherwise the first shift will occur at the next + time-out of T2 after a read or write of the SR. Data is shifted first into + the low order bit of SR and is then shifted into the next higher order bit + of the shift register on the negative-going edge of each clock pulse. The + input data should change before the positive-going edge of the CB1 clock + pulse. This data is shifted into shift register during the 02 clock cycle + following the positive-going edge of the CB1 clock pulse. After 8 CB1 clock + pulses, the shift register interrupt flag will set and IRQ will go low. + */ + } + + func testShiftInUnderPhase2() { + /* + In mode 2, the shift rate is a direct function of the system clock + frequency (Figure 23). CB1 becomes an output which generates shift pulses + for controlling external devices. Timer 2 operates as an independent + interval timer and has no effect on SR. The shifting operation is triggered + by reading or writing the Shift Register. Data is shifted, first into bit 0 + and is then shifted into the next higher order bit of the shift register on + the trailing edge of each 02 clock pulse. After 8 clock pulses, the shift + register interrupt flag will be set, and the output clock pulses on CB1 + will stop. + */ + } + + func testShiftInUnderCB1() { + /* + In mode 3, external pin CB1 becomes an input (Figure 24). This allows an + external device to load the shift register at its own pace. The shift + register counter will interrupt the processor each time 8 bits have been + shifted in. However the shift register counter does not stop the shifting + operation; it acts simply as a pulse counter. Reading or writing the Shift + Register resets the Interrupt Flag and initializes the SR counter to count + another 8 pulses. + + Note that the data is shifted during the first system clock cycle + following the positive-going edge of the CB1 shift pulse. For this reason, + data must be held stable during the first full cycle following CB1 going + high. + */ + } + + func testShiftOutUnderT2FreeRunning() { + /* + Mode 4 is very similar to mode 5 in which the shifting rate is set by T2. + However, in mode 4 the SR Counter does not stop the shifting operation + (Figure 25). Since the Shift Register bit 7 (SR7) is recirculated back into + bit 0, the 8 bits loaded into the Shift Register will be clocked onto CB2 + repetitively. In this mode the Shift Register Counter is disabled. + */ + } + + func testShiftOutUnderT2() { + /* + In mode 5, the shift rate is controlled by T2 (as in mode 4). The shifting + operation is triggered by the read or write of the SR if the SR flag is set + in the IFR (Figure 26). Otherwise the first shift will occur at the next + time-out of T2 after a read or write of the SR. However, with each read or + write of the shift register the SR Counter is reset and 8 bits are shifted + onto CB2. At the same time, 8 shift pulses are generated on CB1 to control + shifting in external devices. After the 8 shift pulses, the shifting is + disabled, the SR Interrupt Flag is set and CB2 remains at the last data + level. + */ + } + + func testShiftOutUnderPhase2() { + /* + In mode 6, the shift rate is controlled by the 02 system clock (Figure 27). + */ + } + + func testShiftOutUnderCB1() { + /* + In mode 7, shifting is controlled by pulses applied to the CB1 pin by an + external device (Figure 28). The SR counter sets the SR Interrupt Flag each + time it counts 8 pulses but it does not disable the shifting function. Each + time the microprocessor, writes or reads the shift register, the SR + Interrupt Flag is reset and the SR counter is initialized to begin counting + the next 8 shift pulses on pin CB1. After 8 shift pulses, the Interrupt + Flag is set. The microprocessor can then load the shift register with the + next byte of data. + */ + } }