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https://github.com/TomHarte/CLK.git
synced 2024-07-17 13:29:02 +00:00
Switch the Macintosh to 68000 mk2.
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8ad1d6b813
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@ -73,7 +73,7 @@ template <Analyser::Static::Macintosh::Target::Model model> class ConcreteMachin
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public MachineTypes::MediaTarget,
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public MachineTypes::MediaTarget,
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public MachineTypes::MouseMachine,
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public MachineTypes::MouseMachine,
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public MachineTypes::MappedKeyboardMachine,
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public MachineTypes::MappedKeyboardMachine,
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public CPU::MC68000::BusHandler,
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public CPU::MC68000Mk2::BusHandler,
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public Zilog::SCC::z8530::Delegate,
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public Zilog::SCC::z8530::Delegate,
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public Activity::Source,
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public Activity::Source,
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public Configurable::Device,
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public Configurable::Device,
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@ -191,9 +191,9 @@ template <Analyser::Static::Macintosh::Target::Model model> class ConcreteMachin
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mc68000_.run_for(cycles);
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mc68000_.run_for(cycles);
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}
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}
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using Microcycle = CPU::MC68000::Microcycle;
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using Microcycle = CPU::MC68000Mk2::Microcycle;
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forceinline HalfCycles perform_bus_operation(const Microcycle &cycle, int) {
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HalfCycles perform_bus_operation(const Microcycle &cycle, int) {
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// Advance time.
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// Advance time.
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advance_time(cycle.length);
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advance_time(cycle.length);
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@ -235,21 +235,21 @@ template <Analyser::Static::Macintosh::Target::Model model> class ConcreteMachin
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// VIA accesses are via address 0xefe1fe + register*512,
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// VIA accesses are via address 0xefe1fe + register*512,
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// which at word precision is 0x77f0ff + register*256.
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// which at word precision is 0x77f0ff + register*256.
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if(cycle.operation & Microcycle::Read) {
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if(cycle.operation & Microcycle::Read) {
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cycle.value->halves.low = via_.read(register_address);
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cycle.value->b = via_.read(register_address);
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} else {
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} else {
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via_.write(register_address, cycle.value->halves.low);
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via_.write(register_address, cycle.value->b);
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}
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}
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if(cycle.operation & Microcycle::SelectWord) cycle.value->halves.high = 0xff;
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if(cycle.operation & Microcycle::SelectWord) cycle.value->w |= 0xff00;
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}
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}
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} return delay;
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} return delay;
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case BusDevice::PhaseRead: {
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case BusDevice::PhaseRead: {
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if(cycle.operation & Microcycle::Read) {
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if(cycle.operation & Microcycle::Read) {
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cycle.value->halves.low = phase_ & 7;
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cycle.value->b = phase_ & 7;
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}
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}
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if(cycle.operation & Microcycle::SelectWord) cycle.value->halves.high = 0xff;
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if(cycle.operation & Microcycle::SelectWord) cycle.value->w |= 0xff00;
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} return delay;
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} return delay;
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case BusDevice::IWM: {
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case BusDevice::IWM: {
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@ -258,12 +258,12 @@ template <Analyser::Static::Macintosh::Target::Model model> class ConcreteMachin
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// The IWM; this is a purely polled device, so can be run on demand.
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// The IWM; this is a purely polled device, so can be run on demand.
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if(cycle.operation & Microcycle::Read) {
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if(cycle.operation & Microcycle::Read) {
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cycle.value->halves.low = iwm_->read(register_address);
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cycle.value->b = iwm_->read(register_address);
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} else {
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} else {
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iwm_->write(register_address, cycle.value->halves.low);
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iwm_->write(register_address, cycle.value->b);
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}
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}
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if(cycle.operation & Microcycle::SelectWord) cycle.value->halves.high = 0xff;
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if(cycle.operation & Microcycle::SelectWord) cycle.value->w |= 0xff00;
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} else {
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} else {
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fill_unmapped(cycle);
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fill_unmapped(cycle);
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}
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}
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@ -280,9 +280,9 @@ template <Analyser::Static::Macintosh::Target::Model model> class ConcreteMachin
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scsi_.write(register_address, 0xff, dma_acknowledge);
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scsi_.write(register_address, 0xff, dma_acknowledge);
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} else {
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} else {
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if(cycle.operation & Microcycle::SelectWord) {
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if(cycle.operation & Microcycle::SelectWord) {
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scsi_.write(register_address, cycle.value->halves.high, dma_acknowledge);
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scsi_.write(register_address, cycle.value->w >> 8, dma_acknowledge);
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} else {
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} else {
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scsi_.write(register_address, cycle.value->halves.low, dma_acknowledge);
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scsi_.write(register_address, cycle.value->b, dma_acknowledge);
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}
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}
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}
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}
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} else {
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} else {
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@ -291,9 +291,9 @@ template <Analyser::Static::Macintosh::Target::Model model> class ConcreteMachin
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const auto result = scsi_.read(register_address, dma_acknowledge);
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const auto result = scsi_.read(register_address, dma_acknowledge);
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if(cycle.operation & Microcycle::SelectWord) {
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if(cycle.operation & Microcycle::SelectWord) {
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// Data is loaded on the top part of the bus only.
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// Data is loaded on the top part of the bus only.
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cycle.value->full = uint16_t((result << 8) | 0xff);
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cycle.value->w = uint16_t((result << 8) | 0xff);
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} else {
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} else {
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cycle.value->halves.low = result;
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cycle.value->b = result;
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}
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}
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}
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}
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}
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}
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@ -309,12 +309,12 @@ template <Analyser::Static::Macintosh::Target::Model model> class ConcreteMachin
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scc_.reset();
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scc_.reset();
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if(cycle.operation & Microcycle::Read) {
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if(cycle.operation & Microcycle::Read) {
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cycle.value->halves.low = 0xff;
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cycle.value->b = 0xff;
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}
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}
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} else {
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} else {
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const auto read = scc_.read(int(address >> 1));
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const auto read = scc_.read(int(address >> 1));
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if(cycle.operation & Microcycle::Read) {
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if(cycle.operation & Microcycle::Read) {
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cycle.value->halves.low = read;
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cycle.value->b = read;
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}
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}
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}
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}
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}
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}
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@ -328,9 +328,9 @@ template <Analyser::Static::Macintosh::Target::Model model> class ConcreteMachin
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if(*cycle.address & 1) {
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if(*cycle.address & 1) {
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if(cycle.operation & Microcycle::Read) {
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if(cycle.operation & Microcycle::Read) {
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scc_.write(int(address >> 1), 0xff);
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scc_.write(int(address >> 1), 0xff);
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cycle.value->halves.low = 0xff;
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cycle.value->b = 0xff;
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} else {
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} else {
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scc_.write(int(address >> 1), cycle.value->halves.low);
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scc_.write(int(address >> 1), cycle.value->b);
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}
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}
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} else {
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} else {
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fill_unmapped(cycle);
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fill_unmapped(cycle);
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@ -373,16 +373,16 @@ template <Analyser::Static::Macintosh::Target::Model model> class ConcreteMachin
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break;
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break;
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case Microcycle::SelectWord | Microcycle::Read:
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case Microcycle::SelectWord | Microcycle::Read:
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cycle.value->full = *reinterpret_cast<uint16_t *>(&memory_base[address]);
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cycle.value->w = *reinterpret_cast<uint16_t *>(&memory_base[address]);
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break;
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break;
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case Microcycle::SelectByte | Microcycle::Read:
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case Microcycle::SelectByte | Microcycle::Read:
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cycle.value->halves.low = memory_base[address];
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cycle.value->b = memory_base[address];
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break;
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break;
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case Microcycle::SelectWord:
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case Microcycle::SelectWord:
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*reinterpret_cast<uint16_t *>(&memory_base[address]) = cycle.value->full;
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*reinterpret_cast<uint16_t *>(&memory_base[address]) = cycle.value->w;
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break;
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break;
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case Microcycle::SelectByte:
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case Microcycle::SelectByte:
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memory_base[address] = cycle.value->halves.low;
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memory_base[address] = cycle.value->b;
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break;
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break;
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}
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}
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@ -771,7 +771,7 @@ template <Analyser::Static::Macintosh::Target::Model model> class ConcreteMachin
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Inputs::QuadratureMouse &mouse_;
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Inputs::QuadratureMouse &mouse_;
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};
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};
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CPU::MC68000::Processor<ConcreteMachine, true> mc68000_;
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CPU::MC68000Mk2::Processor<ConcreteMachine, true, true> mc68000_;
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DriveSpeedAccumulator drive_speed_accumulator_;
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DriveSpeedAccumulator drive_speed_accumulator_;
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IWMActor iwm_;
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IWMActor iwm_;
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