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https://github.com/TomHarte/CLK.git
synced 2025-04-21 18:37:11 +00:00
Stubs in just enough of the 5380 to get a Mac Plus too boot.
This commit is contained in:
Thomas Harte
parent
949c1e1668
commit
a90a74a512
@ -8,11 +8,80 @@
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#include "ncr5380.hpp"
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#include "../../Outputs/Log.hpp"
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using namespace NCR::NCR5380;
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void NCR5380::write(int address, uint8_t value) {
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switch(address & 7) {
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case 0:
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LOG("[SCSI] Set current SCSI bus state to " << PADHEX(2) << value);
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break;
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case 1:
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LOG("[SCSI] Initiator command register set: " << PADHEX(2) << value);
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break;
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case 2:
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LOG("[SCSI] Set mode: " << PADHEX(2) << value);
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mode_ = value;
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break;
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case 3:
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LOG("[SCSI] Set target command: " << PADHEX(2) << value);
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break;
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case 4:
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LOG("[SCSI] Set select enabled: " << PADHEX(2) << value);
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break;
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case 5:
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LOG("[SCSI] Start DMA send: " << PADHEX(2) << value);
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break;
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case 6:
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LOG("[SCSI] Start DMA target receive: " << PADHEX(2) << value);
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break;
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case 7:
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LOG("[SCSI] Start DMA initiator receive: " << PADHEX(2) << value);
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break;
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}
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}
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uint8_t NCR5380::read(int address) {
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switch(address & 7) {
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case 0:
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LOG("[SCSI] Get current SCSI bus state");
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return 0xff;
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case 1:
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LOG("[SCSI] Initiator command register get");
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return 0xff;
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case 2:
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LOG("[SCSI] Get mode");
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return mode_;
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case 3:
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LOG("[SCSI] Get target command");
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return 0xff;
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case 4:
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LOG("[SCSI] Get current bus state");
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return 0xff;
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case 5:
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LOG("[SCSI] Get bus and status");
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return 0x03;
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case 6:
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LOG("[SCSI] Get input data");
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return 0xff;
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case 7:
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LOG("[SCSI] Reset parity/interrupt");
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return 0xff;
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}
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return 0;
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}
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@ -24,6 +24,9 @@ class NCR5380 {
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/*! Reads from @c address. */
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uint8_t read(int address);
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private:
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uint8_t mode_ = 0xff;
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};
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}
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@ -29,6 +29,7 @@
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//#define LOG_TRACE
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#include "../../../Components/5380/ncr5380.hpp"
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#include "../../../Components/6522/6522.hpp"
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#include "../../../Components/8530/z8530.hpp"
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#include "../../../Components/DiskII/IWM.hpp"
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@ -183,8 +184,6 @@ template <Analyser::Static::Macintosh::Target::Model model> class ConcreteMachin
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uint16_t *memory_base = nullptr;
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HalfCycles delay;
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switch(memory_map_[word_address >> 16]) {
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case BusDevice::SCSI:
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printf("SCSI\n");
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default: assert(false);
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case BusDevice::Unassigned:
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@ -234,6 +233,35 @@ template <Analyser::Static::Macintosh::Target::Model model> class ConcreteMachin
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}
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} return delay;
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case BusDevice::SCSI: {
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const int register_address = word_address >> 2; // TODO: this is a guess.
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// Even accesses = read; odd = write.
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if(*cycle.address & 1) {
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// Odd access => this is a write. Data will be in the upper byte.
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if(cycle.operation & Microcycle::Read) {
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scsi_.write(register_address, 0xff);
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} else {
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if(cycle.operation & Microcycle::SelectWord) {
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scsi_.write(register_address, cycle.value->halves.high);
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} else {
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scsi_.write(register_address, cycle.value->halves.low);
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}
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}
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} else {
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// Even access => this is a read.
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if(cycle.operation & Microcycle::Read) {
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const auto result = scsi_.read(register_address);
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if(cycle.operation & Microcycle::SelectWord) {
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// Data is loaded on the top part of the bus only.
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cycle.value->full = (result << 8) | 0xff;
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} else {
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cycle.value->halves.low = result;
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}
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}
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}
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} return delay;
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case BusDevice::SCCReadResetPhase: {
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// Any word access here adjusts phase.
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if(cycle.operation & Microcycle::SelectWord) {
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@ -350,7 +378,7 @@ template <Analyser::Static::Macintosh::Target::Model model> class ConcreteMachin
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case Model::Mac128k:
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case Model::Mac512k:
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case Model::Mac512ke:
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populate_memory_map([rom_is_overlay] (std::function<void(int target, BusDevice device)> map_to) {
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populate_memory_map(0, [rom_is_overlay] (std::function<void(int target, BusDevice device)> map_to) {
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// Addresses up to $80 0000 aren't affected by this bit.
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if(rom_is_overlay) {
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// Up to $60 0000 mirrors of the ROM alternate with unassigned areas every $10 0000 byes.
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@ -367,7 +395,7 @@ template <Analyser::Static::Macintosh::Target::Model model> class ConcreteMachin
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break;
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case Model::MacPlus:
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populate_memory_map([rom_is_overlay] (std::function<void(int target, BusDevice device)> map_to) {
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populate_memory_map(0, [rom_is_overlay] (std::function<void(int target, BusDevice device)> map_to) {
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// Addresses up to $80 0000 aren't affected by this bit.
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if(rom_is_overlay) {
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for(int c = 0; c < 0x580000; c += 0x20000) {
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@ -674,6 +702,7 @@ template <Analyser::Static::Macintosh::Target::Model model> class ConcreteMachin
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VIAPortHandler via_port_handler_;
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Zilog::SCC::z8530 scc_;
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NCR::NCR5380::NCR5380 scsi_;
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HalfCycles via_clock_;
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HalfCycles real_time_clock_;
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@ -704,60 +733,28 @@ template <Analyser::Static::Macintosh::Target::Model model> class ConcreteMachin
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BusDevice memory_map_[128];
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void setup_memory_map() {
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// Apply the power-up memory map, i.e. assume that ROM_is_overlay_ = true.
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// Apply the power-up memory map, i.e. assume that ROM_is_overlay_ = true;
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// start by calling into set_rom_is_overlay to seed everything up to $800000.
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set_rom_is_overlay(true);
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using Model = Analyser::Static::Macintosh::Target::Model;
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switch(model) {
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default: assert(false);
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case Model::Mac128k:
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case Model::Mac512k:
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case Model::Mac512ke:
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populate_memory_map([] (std::function<void(int target, BusDevice device)> map_to) {
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// Up to $60 0000 mirrors of the ROM alternate with unassigned areas every $10 0000 byes.
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for(int c = 0; c < 0x600000; c += 0x100000) {
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map_to(c + 0x100000, (c & 0x100000) ? BusDevice::Unassigned : BusDevice::ROM);
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}
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map_to(0x800000, BusDevice::RAM);
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map_to(0x900000, BusDevice::Unassigned);
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map_to(0xa00000, BusDevice::SCCReadResetPhase);
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map_to(0xb00000, BusDevice::Unassigned);
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map_to(0xc00000, BusDevice::SCCWrite);
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map_to(0xd00000, BusDevice::Unassigned);
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map_to(0xe00000, BusDevice::IWM);
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map_to(0xe80000, BusDevice::Unassigned);
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map_to(0xf00000, BusDevice::VIA);
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map_to(0xf80000, BusDevice::PhaseRead);
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map_to(0x1000000, BusDevice::Unassigned);
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});
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break;
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case Model::MacPlus:
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populate_memory_map([] (std::function<void(int target, BusDevice device)> map_to) {
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for(int c = 0; c < 0x580000; c += 0x20000) {
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map_to(c + 0x20000, ((c & 0x100000) || (c & 0x20000)) ? BusDevice::Unassigned : BusDevice::ROM);
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}
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map_to(0x600000, BusDevice::SCSI);
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map_to(0x800000, BusDevice::RAM);
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map_to(0x900000, BusDevice::Unassigned);
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map_to(0xa00000, BusDevice::SCCReadResetPhase);
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map_to(0xb00000, BusDevice::Unassigned);
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map_to(0xc00000, BusDevice::SCCWrite);
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map_to(0xd00000, BusDevice::Unassigned);
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map_to(0xe00000, BusDevice::IWM);
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map_to(0xe80000, BusDevice::Unassigned);
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map_to(0xf00000, BusDevice::VIA);
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map_to(0xf80000, BusDevice::PhaseRead);
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map_to(0x1000000, BusDevice::Unassigned);
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});
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break;
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}
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populate_memory_map(0x800000, [] (std::function<void(int target, BusDevice device)> map_to) {
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map_to(0x900000, BusDevice::Unassigned);
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map_to(0xa00000, BusDevice::SCCReadResetPhase);
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map_to(0xb00000, BusDevice::Unassigned);
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map_to(0xc00000, BusDevice::SCCWrite);
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map_to(0xd00000, BusDevice::Unassigned);
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map_to(0xe00000, BusDevice::IWM);
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map_to(0xe80000, BusDevice::Unassigned);
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map_to(0xf00000, BusDevice::VIA);
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map_to(0xf80000, BusDevice::PhaseRead);
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map_to(0x1000000, BusDevice::Unassigned);
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});
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}
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void populate_memory_map(std::function<void(std::function<void(int, BusDevice)>)> populator) {
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void populate_memory_map(int start_address, std::function<void(std::function<void(int, BusDevice)>)> populator) {
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// Define semantics for below; map_to will write from the current cursor position
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// to the supplied 24-bit address, setting a particular mapped device.
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int segment = 0;
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int segment = start_address >> 17;
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auto map_to = [&segment, this](int address, BusDevice device) {
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for(; segment < address >> 17; ++segment) {
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this->memory_map_[segment] = device;
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