6502/CLK
1
0
Fork 0
mirror of https://github.com/TomHarte/CLK.git synced 2024-09-27 18:55:48 +00:00
Code Issues Projects Releases Wiki Activity

Ensured that register 6 is checked on every loop.

Browse Source
This commit is contained in:
Thomas Harte 2017-08-22 22:17:45 -04:00
parent 131b340d75
commit a914eadc85
1 changed files with 5 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
Components/6845/CRTC6845.hpp
View File

@ -153,17 +153,17 @@ template <class T> class CRTC6845 {
} else {
line_counter_ = (line_counter_ + 1) & 0x7f;
// check for end of visible lines
if(line_counter_ == registers_[6]) {
line_is_visible_ = false;
}
// check for start of vertical sync
if(line_counter_ == registers_[7]) {
bus_state_.vsync = true;
vsync_down_counter_ = registers_[3] >> 4;
if(!vsync_down_counter_) vsync_down_counter_ = 16;
}
// check for end of visible lines
if(line_counter_ == registers_[6]) {
line_is_visible_ = false;
}
}
} else {
bus_state_.row_address = (bus_state_.row_address + 1) & 0x1f;