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https://github.com/TomHarte/CLK.git
synced 2024-11-26 08:49:37 +00:00
Introduced a scan's delay, as intended.
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cd97617a8a
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@ -170,18 +170,11 @@ CRT::SyncEvent CRT::get_next_horizontal_sync_event(bool hsync_is_requested, unsi
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return proposedEvent;
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}
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void CRT::advance_cycles(unsigned int number_of_cycles, unsigned int source_divider, bool hsync_requested, bool vsync_requested, const bool vsync_charging, const Type type)
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void CRT::advance_cycles(unsigned int number_of_cycles, unsigned int source_divider, bool hsync_requested, bool vsync_requested, const bool vsync_charging, const Type type, uint16_t tex_x, uint16_t tex_y)
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{
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number_of_cycles *= _time_multiplier;
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bool is_output_run = ((type == Type::Level) || (type == Type::Data));
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uint16_t tex_x = 0;
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uint16_t tex_y = 0;
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if(is_output_run && _current_frame_builder) {
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tex_x = _current_frame_builder->_write_x_position;
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tex_y = _current_frame_builder->_write_y_position;
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}
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while(number_of_cycles) {
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@ -344,16 +337,17 @@ void CRT::set_delegate(Delegate *delegate)
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#pragma mark - stream feeding methods
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void CRT::output_scan(Scan *scan)
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void CRT::output_scan()
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{
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_next_scan ^= 1;
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Scan *scan = &_scans[_next_scan];
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bool this_is_sync = (scan->type == Type::Sync);
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bool hsync_requested = !_is_receiving_sync && this_is_sync;
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bool vsync_requested = _is_receiving_sync;
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_is_receiving_sync = this_is_sync;
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advance_cycles(scan->number_of_cycles, scan->source_divider, hsync_requested, vsync_requested, this_is_sync, scan->type);
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_next_scan ^= 1;
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advance_cycles(scan->number_of_cycles, scan->source_divider, hsync_requested, vsync_requested, this_is_sync, scan->type, scan->tex_x, scan->tex_y);
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}
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/*
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@ -363,14 +357,14 @@ void CRT::output_sync(unsigned int number_of_cycles)
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{
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_scans[_next_scan].type = Type::Sync;
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_scans[_next_scan].number_of_cycles = number_of_cycles;
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output_scan(&_scans[_next_scan]);
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output_scan();
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}
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void CRT::output_blank(unsigned int number_of_cycles)
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{
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_scans[_next_scan].type = Type::Blank;
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_scans[_next_scan].number_of_cycles = number_of_cycles;
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output_scan(&_scans[_next_scan]);
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output_scan();
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}
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void CRT::output_level(unsigned int number_of_cycles)
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@ -379,7 +373,7 @@ void CRT::output_level(unsigned int number_of_cycles)
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_scans[_next_scan].number_of_cycles = number_of_cycles;
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_scans[_next_scan].tex_x = _current_frame_builder ? _current_frame_builder->_write_x_position : 0;
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_scans[_next_scan].tex_y = _current_frame_builder ? _current_frame_builder->_write_y_position : 0;
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output_scan(&_scans[_next_scan]);
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output_scan();
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}
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void CRT::output_colour_burst(unsigned int number_of_cycles, uint8_t phase, uint8_t magnitude)
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@ -388,7 +382,7 @@ void CRT::output_colour_burst(unsigned int number_of_cycles, uint8_t phase, uint
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_scans[_next_scan].number_of_cycles = number_of_cycles;
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_scans[_next_scan].phase = phase;
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_scans[_next_scan].magnitude = magnitude;
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output_scan(&_scans[_next_scan]);
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output_scan();
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}
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void CRT::output_data(unsigned int number_of_cycles, unsigned int source_divider)
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@ -398,7 +392,7 @@ void CRT::output_data(unsigned int number_of_cycles, unsigned int source_divider
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_scans[_next_scan].tex_x = _current_frame_builder ? _current_frame_builder->_write_x_position : 0;
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_scans[_next_scan].tex_y = _current_frame_builder ? _current_frame_builder->_write_y_position : 0;
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_scans[_next_scan].source_divider = source_divider;
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output_scan(&_scans[_next_scan]);
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output_scan();
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}
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#pragma mark - Buffer supply
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@ -146,7 +146,7 @@ class CRT {
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enum Type {
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Sync, Level, Data, Blank, ColourBurst
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} type;
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void advance_cycles(unsigned int number_of_cycles, unsigned int source_divider, bool hsync_requested, bool vsync_requested, bool vsync_charging, Type type);
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void advance_cycles(unsigned int number_of_cycles, unsigned int source_divider, bool hsync_requested, bool vsync_requested, const bool vsync_charging, const Type type, uint16_t tex_x, uint16_t tex_y);
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// the inner entry point that determines whether and when the next sync event will occur within
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// the current output window
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@ -173,7 +173,7 @@ class CRT {
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};
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} _scans[2];
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int _next_scan;
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void output_scan(Scan *scan);
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void output_scan();
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};
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}
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