mirror of
https://github.com/TomHarte/CLK.git
synced 2024-09-30 22:56:03 +00:00
Stops trying to force bit ID into the addressing mode.
This commit is contained in:
Thomas Harte
parent
c78c121159
commit
aa478cd222
@ -21,211 +21,211 @@ Instruction Decoder::instrucion_for_opcode(uint8_t opcode) {
|
||||
|
||||
/* 0x00 – 0x0f */
|
||||
Map(0x00, BRK, Implied); Map(0x01, ORA, XIndirect);
|
||||
Map(0x02, JSR, ZeroPageIndirect); Map(0x03, BBS, Bit0AccumulatorRelative);
|
||||
Map(0x02, JSR, ZeroPageIndirect); Map(0x03, BBS0, AccumulatorRelative);
|
||||
|
||||
Map(0x05, ORA, ZeroPage);
|
||||
Map(0x06, ASL, ZeroPage); Map(0x07, BBS, Bit0ZeroPageRelative);
|
||||
Map(0x06, ASL, ZeroPage); Map(0x07, BBS0, ZeroPageRelative);
|
||||
|
||||
Map(0x08, PHP, Implied); Map(0x09, ORA, Immediate);
|
||||
Map(0x0a, ASL, Accumulator); Map(0x0b, SEB, Bit0Accumulator);
|
||||
Map(0x0a, ASL, Accumulator); Map(0x0b, SEB0, Accumulator);
|
||||
|
||||
Map(0x0d, ORA, Absolute);
|
||||
Map(0x0e, ASL, Absolute); Map(0x0f, SEB, Bit0ZeroPage);
|
||||
Map(0x0e, ASL, Absolute); Map(0x0f, SEB0, ZeroPage);
|
||||
|
||||
/* 0x10 – 0x1f */
|
||||
Map(0x10, BPL, Relative); Map(0x11, ORA, IndirectY);
|
||||
Map(0x12, CLT, Implied); Map(0x13, BBC, Bit0AccumulatorRelative);
|
||||
Map(0x12, CLT, Implied); Map(0x13, BBC0, AccumulatorRelative);
|
||||
|
||||
Map(0x15, ORA, ZeroPageX);
|
||||
Map(0x16, ASL, ZeroPageX); Map(0x17, BBC, Bit0ZeroPageRelative);
|
||||
Map(0x16, ASL, ZeroPageX); Map(0x17, BBC0, ZeroPageRelative);
|
||||
|
||||
Map(0x18, CLC, Implied); Map(0x19, ORA, AbsoluteY);
|
||||
Map(0x1a, DEC, Accumulator); Map(0x1b, CLB, Bit0Accumulator);
|
||||
Map(0x1a, DEC, Accumulator); Map(0x1b, CLB0, Accumulator);
|
||||
|
||||
Map(0x1d, ORA, AbsoluteX);
|
||||
Map(0x1e, ASL, AbsoluteX); Map(0x1f, CLB, Bit0ZeroPage);
|
||||
Map(0x1e, ASL, AbsoluteX); Map(0x1f, CLB0, ZeroPage);
|
||||
|
||||
/* 0x20 – 0x2f */
|
||||
Map(0x20, JSR, Absolute); Map(0x21, AND, XIndirect);
|
||||
Map(0x22, JSR, SpecialPage); Map(0x23, BBS, Bit1AccumulatorRelative);
|
||||
Map(0x22, JSR, SpecialPage); Map(0x23, BBS1, AccumulatorRelative);
|
||||
|
||||
Map(0x24, BIT, ZeroPage); Map(0x25, AND, ZeroPage);
|
||||
Map(0x26, ROL, ZeroPage); Map(0x27, BBS, Bit1ZeroPageRelative);
|
||||
Map(0x26, ROL, ZeroPage); Map(0x27, BBS1, ZeroPageRelative);
|
||||
|
||||
Map(0x28, PLP, Implied); Map(0x29, AND, Immediate);
|
||||
Map(0x2a, ROL, Accumulator); Map(0x2b, SEB, Bit1Accumulator);
|
||||
Map(0x2a, ROL, Accumulator); Map(0x2b, SEB1, Accumulator);
|
||||
|
||||
Map(0x2c, BIT, Absolute); Map(0x2d, AND, Absolute);
|
||||
Map(0x2e, ROL, Absolute); Map(0x2f, SEB, Bit1ZeroPage);
|
||||
Map(0x2e, ROL, Absolute); Map(0x2f, SEB1, ZeroPage);
|
||||
|
||||
/* 0x30 – 0x3f */
|
||||
Map(0x30, BMI, Relative); Map(0x31, AND, IndirectY);
|
||||
Map(0x32, SET, Implied); Map(0x33, BBC, Bit1AccumulatorRelative);
|
||||
Map(0x32, SET, Implied); Map(0x33, BBC1, AccumulatorRelative);
|
||||
|
||||
Map(0x35, AND, ZeroPageX);
|
||||
Map(0x36, ROL, ZeroPageX); Map(0x37, BBC, Bit1ZeroPageRelative);
|
||||
Map(0x36, ROL, ZeroPageX); Map(0x37, BBC1, ZeroPageRelative);
|
||||
|
||||
Map(0x38, SEC, Implied); Map(0x39, AND, AbsoluteY);
|
||||
Map(0x3a, INC, Accumulator); Map(0x3b, CLB, Bit1Accumulator);
|
||||
Map(0x3a, INC, Accumulator); Map(0x3b, CLB1, Accumulator);
|
||||
|
||||
Map(0x3c, LDM, ImmediateZeroPage); Map(0x3d, AND, AbsoluteX);
|
||||
Map(0x3e, ROL, AbsoluteX); Map(0x3f, CLB, Bit1ZeroPage);
|
||||
Map(0x3e, ROL, AbsoluteX); Map(0x3f, CLB1, ZeroPage);
|
||||
|
||||
/* 0x40 – 0x4f */
|
||||
Map(0x40, RTI, Implied); Map(0x41, EOR, XIndirect);
|
||||
Map(0x42, STP, Implied); Map(0x43, BBS, Bit2AccumulatorRelative);
|
||||
Map(0x42, STP, Implied); Map(0x43, BBS2, AccumulatorRelative);
|
||||
|
||||
Map(0x44, COM, ZeroPage); Map(0x45, EOR, ZeroPage);
|
||||
Map(0x46, LSR, ZeroPage); Map(0x47, BBS, Bit2ZeroPageRelative);
|
||||
Map(0x46, LSR, ZeroPage); Map(0x47, BBS2, ZeroPageRelative);
|
||||
|
||||
Map(0x48, PHA, Implied); Map(0x49, EOR, Immediate);
|
||||
Map(0x4a, LSR, Accumulator); Map(0x4b, SEB, Bit2Accumulator);
|
||||
Map(0x4a, LSR, Accumulator); Map(0x4b, SEB2, Accumulator);
|
||||
|
||||
Map(0x4c, JMP, Absolute); Map(0x4d, EOR, Absolute);
|
||||
Map(0x4e, LSR, Absolute); Map(0x4f, SEB, Bit2ZeroPage);
|
||||
Map(0x4e, LSR, Absolute); Map(0x4f, SEB2, ZeroPage);
|
||||
|
||||
/* 0x50 – 0x5f */
|
||||
Map(0x50, BVC, Relative); Map(0x51, EOR, IndirectY);
|
||||
Map(0x53, BBC, Bit2AccumulatorRelative);
|
||||
Map(0x53, BBC2, AccumulatorRelative);
|
||||
|
||||
Map(0x55, EOR, ZeroPageX);
|
||||
Map(0x56, LSR, ZeroPageX); Map(0x57, BBC, Bit2ZeroPageRelative);
|
||||
Map(0x56, LSR, ZeroPageX); Map(0x57, BBC2, ZeroPageRelative);
|
||||
|
||||
Map(0x58, CLI, Implied); Map(0x59, EOR, AbsoluteY);
|
||||
Map(0x5b, CLB, Bit2Accumulator);
|
||||
Map(0x5b, CLB2, Accumulator);
|
||||
|
||||
Map(0x5d, EOR, AbsoluteX);
|
||||
Map(0x5e, LSR, AbsoluteX); Map(0x5f, CLB, Bit2ZeroPage);
|
||||
Map(0x5e, LSR, AbsoluteX); Map(0x5f, CLB2, ZeroPage);
|
||||
|
||||
/* 0x60 – 0x6f */
|
||||
Map(0x60, RTS, Implied); Map(0x61, ADC, XIndirect);
|
||||
Map(0x63, BBS, Bit3AccumulatorRelative);
|
||||
Map(0x63, BBS3, AccumulatorRelative);
|
||||
|
||||
Map(0x64, TST, ZeroPage); Map(0x65, ADC, ZeroPage);
|
||||
Map(0x66, ROR, ZeroPage); Map(0x67, BBS, Bit3ZeroPageRelative);
|
||||
Map(0x66, ROR, ZeroPage); Map(0x67, BBS3, ZeroPageRelative);
|
||||
|
||||
Map(0x68, PLA, Implied); Map(0x69, ADC, Immediate);
|
||||
Map(0x6a, ROR, Accumulator); Map(0x6b, SEB, Bit3Accumulator);
|
||||
Map(0x6a, ROR, Accumulator); Map(0x6b, SEB3, Accumulator);
|
||||
|
||||
Map(0x6c, JMP, AbsoluteIndirect); Map(0x6d, ADC, Absolute);
|
||||
Map(0x6e, ROR, Absolute); Map(0x6f, SEB, Bit3ZeroPage);
|
||||
Map(0x6e, ROR, Absolute); Map(0x6f, SEB3, ZeroPage);
|
||||
|
||||
/* 0x70 – 0x7f */
|
||||
Map(0x70, BVS, Relative); Map(0x71, ADC, IndirectY);
|
||||
Map(0x73, BBC, Bit3AccumulatorRelative);
|
||||
Map(0x73, BBC3, AccumulatorRelative);
|
||||
|
||||
Map(0x75, ADC, ZeroPageX);
|
||||
Map(0x76, ROR, ZeroPageX); Map(0x77, BBC, Bit3ZeroPageRelative);
|
||||
Map(0x76, ROR, ZeroPageX); Map(0x77, BBC3, ZeroPageRelative);
|
||||
|
||||
Map(0x78, SEI, Implied); Map(0x79, ADC, AbsoluteY);
|
||||
Map(0x7b, CLB, Bit3Accumulator);
|
||||
Map(0x7b, CLB3, Accumulator);
|
||||
|
||||
Map(0x7d, ADC, AbsoluteX);
|
||||
Map(0x7e, ROR, AbsoluteX); Map(0x7f, CLB, Bit3ZeroPage);
|
||||
Map(0x7e, ROR, AbsoluteX); Map(0x7f, CLB3, ZeroPage);
|
||||
|
||||
/* 0x80 – 0x8f */
|
||||
Map(0x80, BRA, Relative); Map(0x81, STA, XIndirect);
|
||||
Map(0x82, RRF, ZeroPage); Map(0x83, BBS, Bit4AccumulatorRelative);
|
||||
Map(0x82, RRF, ZeroPage); Map(0x83, BBS4, AccumulatorRelative);
|
||||
|
||||
Map(0x84, STY, ZeroPage); Map(0x85, STA, ZeroPage);
|
||||
Map(0x86, STX, ZeroPage); Map(0x87, BBS, Bit4ZeroPageRelative);
|
||||
Map(0x86, STX, ZeroPage); Map(0x87, BBS4, ZeroPageRelative);
|
||||
|
||||
Map(0x88, DEY, Implied);
|
||||
Map(0x8a, TXA, Implied); Map(0x8b, SEB, Bit4Accumulator);
|
||||
Map(0x8a, TXA, Implied); Map(0x8b, SEB4, Accumulator);
|
||||
|
||||
Map(0x8c, STY, Absolute); Map(0x8d, STA, Absolute);
|
||||
Map(0x8e, STX, Absolute); Map(0x8f, SEB, Bit4ZeroPage);
|
||||
Map(0x8e, STX, Absolute); Map(0x8f, SEB4, ZeroPage);
|
||||
|
||||
/* 0x90 – 0x9f */
|
||||
Map(0x90, BCC, Relative); Map(0x91, STA, IndirectY);
|
||||
Map(0x93, BBC, Bit4AccumulatorRelative);
|
||||
Map(0x93, BBC4, AccumulatorRelative);
|
||||
|
||||
Map(0x94, STY, ZeroPageX); Map(0x95, STA, ZeroPageX);
|
||||
Map(0x96, STX, ZeroPageX); Map(0x97, BBC, Bit4ZeroPageRelative);
|
||||
Map(0x96, STX, ZeroPageX); Map(0x97, BBC4, ZeroPageRelative);
|
||||
|
||||
Map(0x98, TYA, Implied); Map(0x99, STA, AbsoluteY);
|
||||
Map(0x9a, TXS, AbsoluteY); Map(0x9b, CLB, Bit4Accumulator);
|
||||
Map(0x9a, TXS, AbsoluteY); Map(0x9b, CLB4, Accumulator);
|
||||
|
||||
Map(0x9d, ADC, AbsoluteX);
|
||||
Map(0x9f, CLB, Bit4ZeroPage);
|
||||
Map(0x9f, CLB4, ZeroPage);
|
||||
|
||||
/* 0xa0 – 0xaf */
|
||||
Map(0xa0, LDY, Immediate); Map(0xa1, LDA, XIndirect);
|
||||
Map(0xa2, LDX, Immediate); Map(0xa3, BBS, Bit5AccumulatorRelative);
|
||||
Map(0xa2, LDX, Immediate); Map(0xa3, BBS5, AccumulatorRelative);
|
||||
|
||||
Map(0xa4, LDY, ZeroPage); Map(0xa5, LDA, ZeroPage);
|
||||
Map(0xa6, LDX, ZeroPage); Map(0xa7, BBS, Bit5ZeroPageRelative);
|
||||
Map(0xa6, LDX, ZeroPage); Map(0xa7, BBS5, ZeroPageRelative);
|
||||
|
||||
Map(0xa8, TAY, Implied); Map(0xa9, LDA, Immediate);
|
||||
Map(0xaa, TAX, Implied); Map(0xab, SEB, Bit5Accumulator);
|
||||
Map(0xaa, TAX, Implied); Map(0xab, SEB5, Accumulator);
|
||||
|
||||
Map(0xac, LDY, Absolute); Map(0xad, LDA, Absolute);
|
||||
Map(0xae, LDX, Absolute); Map(0xaf, SEB, Bit5ZeroPage);
|
||||
Map(0xae, LDX, Absolute); Map(0xaf, SEB5, ZeroPage);
|
||||
|
||||
/* 0xb0 – 0xbf */
|
||||
Map(0xb0, BCS, Relative); Map(0xb1, STA, IndirectY);
|
||||
Map(0xb2, JMP, ZeroPageIndirect); Map(0xb3, BBC, Bit5AccumulatorRelative);
|
||||
Map(0xb2, JMP, ZeroPageIndirect); Map(0xb3, BBC5, AccumulatorRelative);
|
||||
|
||||
Map(0xb4, LDY, ZeroPageX); Map(0xb5, LDA, ZeroPageX);
|
||||
Map(0xb6, LDX, ZeroPageY); Map(0xb7, BBC, Bit5ZeroPageRelative);
|
||||
Map(0xb6, LDX, ZeroPageY); Map(0xb7, BBC5, ZeroPageRelative);
|
||||
|
||||
Map(0xb8, CLV, Implied); Map(0xb9, LDA, AbsoluteY);
|
||||
Map(0xba, TSX, AbsoluteY); Map(0xbb, CLB, Bit5Accumulator);
|
||||
Map(0xba, TSX, AbsoluteY); Map(0xbb, CLB5, Accumulator);
|
||||
|
||||
Map(0xbc, LDY, AbsoluteX); Map(0xbd, LDA, AbsoluteX);
|
||||
Map(0xbe, LDX, AbsoluteY); Map(0xbf, CLB, Bit5ZeroPage);
|
||||
Map(0xbe, LDX, AbsoluteY); Map(0xbf, CLB5, ZeroPage);
|
||||
|
||||
/* 0xc0 – 0xcf */
|
||||
Map(0xc0, CPY, Immediate); Map(0xc1, CMP, XIndirect);
|
||||
Map(0xc2, SLW, Implied); Map(0xc3, BBS, Bit6AccumulatorRelative);
|
||||
Map(0xc2, SLW, Implied); Map(0xc3, BBS6, AccumulatorRelative);
|
||||
|
||||
Map(0xc4, CPY, ZeroPage); Map(0xc5, CMP, ZeroPage);
|
||||
Map(0xc6, DEC, ZeroPage); Map(0xc7, BBS, Bit6ZeroPageRelative);
|
||||
Map(0xc6, DEC, ZeroPage); Map(0xc7, BBS6, ZeroPageRelative);
|
||||
|
||||
Map(0xc8, INY, Implied); Map(0xc9, CMP, Immediate);
|
||||
Map(0xca, DEX, Implied); Map(0xcb, SEB, Bit6Accumulator);
|
||||
Map(0xca, DEX, Implied); Map(0xcb, SEB6, Accumulator);
|
||||
|
||||
Map(0xcc, CPY, Absolute); Map(0xcd, CMP, Absolute);
|
||||
Map(0xce, DEC, Absolute); Map(0xcf, SEB, Bit6ZeroPage);
|
||||
Map(0xce, DEC, Absolute); Map(0xcf, SEB6, ZeroPage);
|
||||
|
||||
/* 0xd0 – 0xdf */
|
||||
Map(0xd0, BNE, Relative); Map(0xd1, CMP, IndirectY);
|
||||
Map(0xd3, BBC, Bit6AccumulatorRelative);
|
||||
Map(0xd3, BBC6, AccumulatorRelative);
|
||||
|
||||
Map(0xd5, CMP, ZeroPageX);
|
||||
Map(0xd6, DEC, ZeroPageX); Map(0xd7, BBC, Bit6ZeroPageRelative);
|
||||
Map(0xd6, DEC, ZeroPageX); Map(0xd7, BBC6, ZeroPageRelative);
|
||||
|
||||
Map(0xd8, CLD, Implied); Map(0xd9, CMP, AbsoluteY);
|
||||
Map(0xdb, CLB, Bit6Accumulator);
|
||||
Map(0xdb, CLB6, Accumulator);
|
||||
|
||||
Map(0xdd, CMP, AbsoluteX);
|
||||
Map(0xde, DEC, AbsoluteX); Map(0xdf, CLB, Bit6ZeroPage);
|
||||
Map(0xde, DEC, AbsoluteX); Map(0xdf, CLB6, ZeroPage);
|
||||
|
||||
/* 0xe0 – 0xef */
|
||||
Map(0xe0, CPX, Immediate); Map(0xe1, SBC, XIndirect);
|
||||
Map(0xe2, FST, Implied); Map(0xe3, BBS, Bit7AccumulatorRelative);
|
||||
Map(0xe2, FST, Implied); Map(0xe3, BBS7, AccumulatorRelative);
|
||||
|
||||
Map(0xe4, CPX, ZeroPage); Map(0xe5, SBC, ZeroPage);
|
||||
Map(0xe6, INC, ZeroPage); Map(0xe7, BBS, Bit7ZeroPageRelative);
|
||||
Map(0xe6, INC, ZeroPage); Map(0xe7, BBS7, ZeroPageRelative);
|
||||
|
||||
Map(0xe8, INX, Implied); Map(0xe9, SBC, Immediate);
|
||||
Map(0xea, NOP, Implied); Map(0xeb, SEB, Bit7Accumulator);
|
||||
Map(0xea, NOP, Implied); Map(0xeb, SEB7, Accumulator);
|
||||
|
||||
Map(0xec, CPX, Absolute); Map(0xed, SBC, Absolute);
|
||||
Map(0xee, INC, Absolute); Map(0xef, SEB, Bit7ZeroPage);
|
||||
Map(0xee, INC, Absolute); Map(0xef, SEB7, ZeroPage);
|
||||
|
||||
/* 0xf0 – 0xff */
|
||||
Map(0xf0, BEQ, Relative); Map(0xf1, SBC, IndirectY);
|
||||
Map(0xf3, BBC, Bit7AccumulatorRelative);
|
||||
Map(0xf3, BBC7, AccumulatorRelative);
|
||||
|
||||
Map(0xf5, SBC, ZeroPageX);
|
||||
Map(0xf6, INC, ZeroPageX); Map(0xf7, BBC, Bit7ZeroPageRelative);
|
||||
Map(0xf6, INC, ZeroPageX); Map(0xf7, BBC7, ZeroPageRelative);
|
||||
|
||||
Map(0xf8, SED, Implied); Map(0xf9, SBC, AbsoluteY);
|
||||
Map(0xfb, CLB, Bit7Accumulator);
|
||||
Map(0xfb, CLB7, Accumulator);
|
||||
|
||||
Map(0xfd, SBC, AbsoluteX);
|
||||
Map(0xfe, INC, AbsoluteX); Map(0xff, CLB, Bit7ZeroPage);
|
||||
Map(0xfe, INC, AbsoluteX); Map(0xff, CLB7, ZeroPage);
|
||||
|
||||
#undef Map
|
||||
}
|
||||
|
||||
@ -76,10 +76,25 @@ template <Operation operation, AddressingMode addressing_mode> void Executor::pe
|
||||
program_counter_ += 2;
|
||||
return;
|
||||
|
||||
case AddressingMode::Relative:
|
||||
// case AddressingMode::Relative:
|
||||
// These are all the branches...
|
||||
// address = program_counter_ + size(addressing_mode) + int8_t(next8());
|
||||
return;
|
||||
// return;
|
||||
|
||||
// case AddressingMode::ImmediateZeroPage:
|
||||
// LDM only...
|
||||
// return;
|
||||
|
||||
// case AddressingMode::SpecialPage: address = 0x1f00 | next8(); break;
|
||||
// JSR only...
|
||||
|
||||
/* TODO:
|
||||
|
||||
AccumulatorRelative
|
||||
ZeroPageRelative
|
||||
|
||||
... which are BBC/BBS-exclusive.
|
||||
*/
|
||||
|
||||
// Addressing modes with a memory access.
|
||||
|
||||
@ -89,7 +104,6 @@ template <Operation operation, AddressingMode addressing_mode> void Executor::pe
|
||||
case AddressingMode::ZeroPage: address = next8(); break;
|
||||
case AddressingMode::ZeroPageX: address = (next8() + x_) & 0xff; break;
|
||||
case AddressingMode::ZeroPageY: address = (next8() + x_) & 0xff; break;
|
||||
case AddressingMode::SpecialPage: address = 0x1f00 | next8(); break;
|
||||
|
||||
case AddressingMode::ZeroPageIndirect:
|
||||
address = next8();
|
||||
@ -110,16 +124,6 @@ template <Operation operation, AddressingMode addressing_mode> void Executor::pe
|
||||
address = memory_[address] | (memory_[(address + 1) & 0x1fff] << 8);
|
||||
break;
|
||||
|
||||
/* TODO:
|
||||
|
||||
ImmediateZeroPage (for LDM)
|
||||
BitXAccumulator
|
||||
BitXZeroPage
|
||||
BitXAccumulatorRelative
|
||||
BitXZeroPageRelative
|
||||
*/
|
||||
|
||||
|
||||
default:
|
||||
assert(false);
|
||||
}
|
||||
@ -145,17 +149,33 @@ template <Operation operation, AddressingMode addressing_mode> void Executor::pe
|
||||
}
|
||||
|
||||
template <Operation operation> void Executor::perform(uint8_t *operand [[maybe_unused]]) {
|
||||
#define set_nz(a) negative_result_ = zero_result_ = (a)
|
||||
switch(operation) {
|
||||
case Operation::LDA: a_ = *operand; break; // TODO: flags (for all three here).
|
||||
case Operation::LDX: x_ = *operand; break;
|
||||
case Operation::LDY: y_ = *operand; break;
|
||||
case Operation::LDA: set_nz(a_ = *operand); break;
|
||||
case Operation::LDX: set_nz(x_ = *operand); break;
|
||||
case Operation::LDY: set_nz(y_ = *operand); break;
|
||||
|
||||
case Operation::STA: *operand = a_; break;
|
||||
case Operation::STX: *operand = x_; break;
|
||||
case Operation::STY: *operand = y_; break;
|
||||
|
||||
default: assert(false);
|
||||
case Operation::SEB0: case Operation::SEB1: case Operation::SEB2: case Operation::SEB3:
|
||||
case Operation::SEB4: case Operation::SEB5: case Operation::SEB6: case Operation::SEB7:
|
||||
*operand |= 1 << (int(operation) - int(Operation::SEB0));
|
||||
break;
|
||||
case Operation::CLB0: case Operation::CLB1: case Operation::CLB2: case Operation::CLB3:
|
||||
case Operation::CLB4: case Operation::CLB5: case Operation::CLB6: case Operation::CLB7:
|
||||
*operand &= ~(1 << (int(operation) - int(Operation::CLB0)));
|
||||
break;
|
||||
|
||||
case Operation::CLI: interrupt_disable_ = 0x00; break;
|
||||
case Operation::SEI: interrupt_disable_ = 0xff; break;
|
||||
|
||||
default:
|
||||
printf("Unimplemented operation: %d\n", int(operation));
|
||||
assert(false);
|
||||
}
|
||||
#undef set_nz
|
||||
}
|
||||
|
||||
void Executor::set_program_counter(uint16_t address) {
|
||||
|
||||
@ -110,7 +110,11 @@ class Executor: public CachingExecutor {
|
||||
|
||||
// Registers.
|
||||
uint16_t program_counter_;
|
||||
uint8_t a_, x_, y_;
|
||||
uint8_t a_, x_, y_, s_;
|
||||
|
||||
uint8_t negative_result_ = 0;
|
||||
uint8_t zero_result_ = 0;
|
||||
uint8_t interrupt_disable_ = 0;
|
||||
};
|
||||
|
||||
}
|
||||
|
||||
@ -21,24 +21,13 @@ enum class AddressingMode {
|
||||
ZeroPage, ZeroPageX, ZeroPageY,
|
||||
XIndirect, IndirectY,
|
||||
Relative,
|
||||
AbsoluteIndirect, ZeroPageIndirect,
|
||||
AbsoluteIndirect, ZeroPageIndirect,
|
||||
SpecialPage,
|
||||
ImmediateZeroPage,
|
||||
|
||||
Bit0Accumulator, Bit1Accumulator, Bit2Accumulator, Bit3Accumulator,
|
||||
Bit4Accumulator, Bit5Accumulator, Bit6Accumulator, Bit7Accumulator,
|
||||
|
||||
Bit0ZeroPage, Bit1ZeroPage, Bit2ZeroPage, Bit3ZeroPage,
|
||||
Bit4ZeroPage, Bit5ZeroPage, Bit6ZeroPage, Bit7ZeroPage,
|
||||
|
||||
Bit0AccumulatorRelative, Bit1AccumulatorRelative, Bit2AccumulatorRelative, Bit3AccumulatorRelative,
|
||||
Bit4AccumulatorRelative, Bit5AccumulatorRelative, Bit6AccumulatorRelative, Bit7AccumulatorRelative,
|
||||
|
||||
Bit0ZeroPageRelative, Bit1ZeroPageRelative, Bit2ZeroPageRelative, Bit3ZeroPageRelative,
|
||||
Bit4ZeroPageRelative, Bit5ZeroPageRelative, Bit6ZeroPageRelative, Bit7ZeroPageRelative,
|
||||
AccumulatorRelative, ZeroPageRelative
|
||||
};
|
||||
|
||||
static constexpr auto MaxAddressingMode = int(AddressingMode::Bit7ZeroPageRelative);
|
||||
static constexpr auto MaxAddressingMode = int(AddressingMode::ZeroPageRelative);
|
||||
static constexpr auto MinAddressingMode = int(AddressingMode::Implied);
|
||||
|
||||
constexpr int size(AddressingMode mode) {
|
||||
@ -52,14 +41,7 @@ constexpr int size(AddressingMode mode) {
|
||||
2, 1,
|
||||
1,
|
||||
2,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
1, 1, 1, 1,
|
||||
1, 1, 1, 1,
|
||||
1, 1, 1, 1,
|
||||
1, 1, 1, 1,
|
||||
2, 2, 2, 2,
|
||||
2, 2, 2, 2,
|
||||
1, 2
|
||||
};
|
||||
static_assert(sizeof(sizes)/sizeof(*sizes) == int(MaxAddressingMode) + 1);
|
||||
return sizes[int(mode)];
|
||||
@ -69,7 +51,9 @@ enum class Operation: uint8_t {
|
||||
Invalid,
|
||||
|
||||
// Operations that don't access memory.
|
||||
BBC, BBS, BCC, BCS,
|
||||
BBC0, BBS0, BBC1, BBS1, BBC2, BBS2, BBC3, BBS3,
|
||||
BBC4, BBS4, BBC5, BBS5, BBC6, BBS6, BBC7, BBS7,
|
||||
BCC, BCS,
|
||||
BEQ, BMI, BNE, BPL,
|
||||
BVC, BVS, BRA, BRK,
|
||||
JMP, JSR,
|
||||
@ -93,7 +77,8 @@ enum class Operation: uint8_t {
|
||||
|
||||
// Read-modify-write operations.
|
||||
ASL, LSR,
|
||||
CLB, SEB,
|
||||
CLB0, SEB0, CLB1, SEB1, CLB2, SEB2, CLB3, SEB3,
|
||||
CLB4, SEB4, CLB5, SEB5, CLB6, SEB6, CLB7, SEB7,
|
||||
COM,
|
||||
DEC, INC,
|
||||
ROL, ROR, RRF,
|
||||
@ -104,7 +89,7 @@ enum class Operation: uint8_t {
|
||||
};
|
||||
|
||||
static constexpr auto MaxOperation = int(Operation::STY);
|
||||
static constexpr auto MinOperation = int(Operation::BBC);
|
||||
static constexpr auto MinOperation = int(Operation::BBC0);
|
||||
|
||||
constexpr AccessType access_type(Operation operation) {
|
||||
if(operation < Operation::ADC) return AccessType::None;
|
||||
|
||||
@ -57,7 +57,7 @@ template<typename Target, bool include_entries_and_accesses> struct Parser {
|
||||
return;
|
||||
|
||||
// Instructions that suggest another entry point but don't terminate parsing.
|
||||
case Operation::BBS: case Operation::BBC:
|
||||
// case Operation::BBS: case Operation::BBC: // TODO: BBS, BBC
|
||||
case Operation::BCC: case Operation::BCS:
|
||||
case Operation::BVC: case Operation::BVS:
|
||||
case Operation::BMI: case Operation::BPL:
|
||||
@ -68,6 +68,16 @@ template<typename Target, bool include_entries_and_accesses> struct Parser {
|
||||
target.add_entry(storage[start + 1] | (storage[start + 2] << 8));
|
||||
break;
|
||||
|
||||
// // TODO: addressing like the below for the relevant BBC and BBS.
|
||||
// case AddressingMode::Bit0AccumulatorRelative:
|
||||
// target.add_access(start + 2 + int8_t(storage[start + 1]), access_type(next.second.operation));
|
||||
// break;
|
||||
|
||||
// // TODO: this is a potential addressing mode for JSR.
|
||||
// case AddressingMode::SpecialPage:
|
||||
// target.add_access(storage[start + 1] | 0x1f00, access_type(next.second.operation));
|
||||
// break;
|
||||
|
||||
default: break;
|
||||
}
|
||||
|
||||
@ -77,21 +87,11 @@ template<typename Target, bool include_entries_and_accesses> struct Parser {
|
||||
target.add_access(storage[start + 1] | (storage[start + 2] << 8), access_type(next.second.operation));
|
||||
break;
|
||||
case AddressingMode::ZeroPage:
|
||||
case AddressingMode::Bit0ZeroPage: case AddressingMode::Bit1ZeroPage:
|
||||
case AddressingMode::Bit2ZeroPage: case AddressingMode::Bit3ZeroPage:
|
||||
case AddressingMode::Bit4ZeroPage: case AddressingMode::Bit5ZeroPage:
|
||||
case AddressingMode::Bit6ZeroPage: case AddressingMode::Bit7ZeroPage:
|
||||
target.add_access(storage[start + 1], access_type(next.second.operation));
|
||||
break;
|
||||
case AddressingMode::SpecialPage:
|
||||
target.add_access(storage[start + 1] | 0x1f00, access_type(next.second.operation));
|
||||
break;
|
||||
case AddressingMode::ImmediateZeroPage:
|
||||
target.add_access(storage[start + 2], access_type(next.second.operation));
|
||||
break;
|
||||
case AddressingMode::Bit0AccumulatorRelative:
|
||||
target.add_access(start + 2 + int8_t(storage[start + 1]), access_type(next.second.operation));
|
||||
break;
|
||||
|
||||
default: break;
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user