diff --git a/Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp b/Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp
index 6978a09e7..cc7a9f863 100644
--- a/Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp
+++ b/Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp
@@ -202,11 +202,14 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
 		//
 		// TODO: add MOVE special case, somewhere.
 		case State::FetchOperand:
-			switch(instruction_.mode(next_operand_)) {
-				case Mode::None:
-					state_ = perform_state_;
+			// Check that this operand is meant to be fetched.
+			if(!(operand_flags_ & (1 << next_operand_))) {
+				state_ = perform_state_;
 				continue;
+			}
 
+			// Figure out how to fetch it.
+			switch(instruction_.mode(next_operand_)) {
 				case Mode::AddressRegisterDirect:
 				case Mode::DataRegisterDirect:
 					operand_[next_operand_] = registers_[instruction_.lreg(next_operand_)];
@@ -295,6 +298,10 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
 	switch(instruction_.operation) {
 		BIND(NBCD, instruction_.mode(0) == Mode::DataRegisterDirect ? State::Perform_np_n : State::Perform_np);
 
+		// MOVEs are a special case for having an operand they write but did not read. So they segue into a
+		// specialised state for writing the result.
+		BIND(MOVEw, State::MOVEWrite);
+
 		default:
 			assert(false);
 	}
diff --git a/Processors/68000Mk2/Implementation/68000Mk2Storage.hpp b/Processors/68000Mk2/Implementation/68000Mk2Storage.hpp
index 3819b3952..1ac5529ce 100644
--- a/Processors/68000Mk2/Implementation/68000Mk2Storage.hpp
+++ b/Processors/68000Mk2/Implementation/68000Mk2Storage.hpp
@@ -37,6 +37,10 @@ struct ProcessorBase: public InstructionSet::M68k::NullFlowController {
 
 		Perform_np		= -6,
 		Perform_np_n	= -7,
+
+		// MOVE has unique bus usage, so has a specialised state.
+
+		MOVEWrite		= -8,
 	};
 	int state_ = State::Reset;