mirror of
https://github.com/TomHarte/CLK.git
synced 2025-01-20 05:30:35 +00:00
Eliminate Objective-C-style naming.
This commit is contained in:
parent
828c2a6883
commit
ace7e24dfb
@ -250,7 +250,7 @@ public:
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}
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if(address < 0x8000) {
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if(isReadOperation(operation)) {
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if(is_read(operation)) {
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*value = ram_[address];
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} else {
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ram_[address] = *value;
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@ -258,7 +258,7 @@ public:
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} else {
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switch(address & 0xff0f) {
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case 0xfe00:
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if(isReadOperation(operation)) {
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if(is_read(operation)) {
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*value = interrupt_status_;
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interrupt_status_ &= ~PowerOnReset;
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} else {
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@ -267,7 +267,7 @@ public:
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}
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break;
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case 0xfe07:
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if(!isReadOperation(operation)) {
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if(!is_read(operation)) {
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// update speaker mode
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bool new_speaker_is_enabled = (*value & 6) == 2;
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if(new_speaker_is_enabled != speaker_is_enabled_) {
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@ -291,12 +291,12 @@ public:
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case 0xfe02: case 0xfe03:
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case 0xfe08: case 0xfe09: case 0xfe0a: case 0xfe0b:
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case 0xfe0c: case 0xfe0d: case 0xfe0e: case 0xfe0f:
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if(!isReadOperation(operation)) {
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if(!is_read(operation)) {
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video_.write(address, *value);
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}
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break;
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case 0xfe04:
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if(isReadOperation(operation)) {
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if(is_read(operation)) {
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*value = tape_.get_data_register();
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tape_.clear_interrupts(Interrupt::ReceiveDataFull);
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} else {
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@ -305,7 +305,7 @@ public:
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}
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break;
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case 0xfe05:
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if(!isReadOperation(operation)) {
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if(!is_read(operation)) {
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const uint8_t interruptDisable = (*value)&0xf0;
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if( interruptDisable ) {
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if( interruptDisable&0x10 ) interrupt_status_ &= ~Interrupt::DisplayEnd;
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@ -332,7 +332,7 @@ public:
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}
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break;
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case 0xfe06:
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if(!isReadOperation(operation)) {
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if(!is_read(operation)) {
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update_audio();
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sound_generator_.set_divider(*value);
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tape_.set_counter(*value);
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@ -345,7 +345,7 @@ public:
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is_holding_shift_ = false;
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set_key_state(KeyShift, false);
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}
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if(isReadOperation(operation))
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if(is_read(operation))
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*value = plus3_->read(address);
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else
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plus3_->write(address, *value);
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@ -353,14 +353,14 @@ public:
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break;
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case 0xfc00:
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if(plus3_ && (address&0x00f0) == 0x00c0) {
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if(!isReadOperation(operation)) {
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if(!is_read(operation)) {
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plus3_->set_control_register(*value);
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} else *value = 1;
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}
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if(has_scsi_bus && (address&0x00f0) == 0x0040) {
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scsi_acknowledge_ = true;
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if(!isReadOperation(operation)) {
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if(!is_read(operation)) {
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scsi_data_ = *value;
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push_scsi_output();
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} else {
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@ -377,7 +377,7 @@ public:
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}
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break;
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case 0xfc01:
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if(has_scsi_bus && (address&0x00f0) == 0x0040 && isReadOperation(operation)) {
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if(has_scsi_bus && (address&0x00f0) == 0x0040 && is_read(operation)) {
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// Status byte is:
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//
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// b7: SCSI C/D
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@ -427,7 +427,7 @@ public:
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default:
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if(address >= 0xc000) {
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if(isReadOperation(operation)) {
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if(is_read(operation)) {
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if(
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use_fast_tape_hack_ &&
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(operation == CPU::MOS6502::BusOperation::ReadOpcode) &&
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@ -479,7 +479,7 @@ public:
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}
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}
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} else {
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if(isReadOperation(operation)) {
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if(is_read(operation)) {
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*value = roms_[active_rom_][address & 16383];
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if(keyboard_is_active_) {
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*value &= 0xf0;
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@ -722,14 +722,14 @@ public:
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bool has_updated_cards = false;
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if(read_pages_[address >> 8]) {
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if(isReadOperation(operation)) *value = read_pages_[address >> 8][address & 0xff];
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if(is_read(operation)) *value = read_pages_[address >> 8][address & 0xff];
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else {
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if(address >= 0x200 && address < 0x6000) update_video();
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if(write_pages_[address >> 8]) write_pages_[address >> 8][address & 0xff] = *value;
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}
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if(is_iie(model)) {
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auxiliary_switches_.access(address, isReadOperation(operation));
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auxiliary_switches_.access(address, is_read(operation));
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}
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} else {
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// Assume a vapour read unless it turns out otherwise; this is a little
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@ -745,7 +745,7 @@ public:
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// doesn't. The call into the video isn't free because it's a just-in-time
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// actor, but this will actually be the result most of the time so it's not
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// too terrible.
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if(isReadOperation(operation) && address != 0xc000) {
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if(is_read(operation) && address != 0xc000) {
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// Ensure any enqueued video changes are applied before grabbing the
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// vapour value.
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if(video_.has_deferred_actions()) {
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@ -756,7 +756,7 @@ public:
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switch(address) {
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default:
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if(isReadOperation(operation)) {
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if(is_read(operation)) {
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// Read-only switches.
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switch(address) {
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default: break;
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@ -868,13 +868,13 @@ public:
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case 0xc055:
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update_video();
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video_.set_page2(address&1);
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auxiliary_switches_.access(address, isReadOperation(operation));
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auxiliary_switches_.access(address, is_read(operation));
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break;
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case 0xc056:
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case 0xc057:
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update_video();
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video_.set_high_resolution(address&1);
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auxiliary_switches_.access(address, isReadOperation(operation));
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auxiliary_switches_.access(address, is_read(operation));
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break;
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case 0xc05e:
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@ -889,7 +889,7 @@ public:
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keyboard_.clear_keyboard_input();
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// On the IIe, reading C010 returns additional key info.
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if(is_iie(model) && isReadOperation(operation)) {
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if(is_iie(model) && is_read(operation)) {
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*value = (keyboard_.get_key_is_down() ? 0x80 : 0x00) | (keyboard_.get_keyboard_input() & 0x7f);
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}
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break;
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@ -904,7 +904,7 @@ public:
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case 0xc081: case 0xc085: case 0xc089: case 0xc08d:
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case 0xc082: case 0xc086: case 0xc08a: case 0xc08e:
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case 0xc083: case 0xc087: case 0xc08b: case 0xc08f:
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language_card_.access(address, isReadOperation(operation));
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language_card_.access(address, is_read(operation));
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break;
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}
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@ -950,7 +950,7 @@ public:
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// If the selected card is a just-in-time card, update the just-in-time cards,
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// and then message it specifically.
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const bool is_read = isReadOperation(operation);
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const bool is_read = CPU::MOS6502Esque::is_read(operation);
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Apple::II::Card *const target = cards_[size_t(card_number)].get();
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if(target && !is_every_cycle_card(target)) {
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update_just_in_time_cards();
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@ -971,7 +971,7 @@ public:
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if(!has_updated_cards && !every_cycle_cards_.empty()) {
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// Update all every-cycle cards and give them the cycle.
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const bool is_read = isReadOperation(operation);
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const bool is_read = CPU::MOS6502Esque::is_read(operation);
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for(const auto &card: every_cycle_cards_) {
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card->run_for(Cycles(1), is_stretched_cycle);
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card->perform_bus_operation(Apple::II::Card::None, is_read, address, value);
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@ -284,7 +284,7 @@ public:
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*value = rom_[rom_.size() - 65536 + address];
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} else if(region.flags & MemoryMap::Region::IsIO) {
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// Ensure classic auxiliary and language card accesses have effect.
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const bool is_read = isReadOperation(operation);
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const bool is_read = CPU::MOS6502Esque::is_read(operation);
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memory_.access(uint16_t(address), is_read);
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const auto address_suffix = address & 0xffff;
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@ -818,7 +818,7 @@ public:
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assert(operation != CPU::WDC65816::BusOperation::ReadOpcode || region.read);
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is_1Mhz = region.flags & MemoryMap::Region::Is1Mhz;
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if(isReadOperation(operation)) {
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if(is_read(operation)) {
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*value = memory_.read(region, address);
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} else {
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// Shadowed writes also occur "at 1Mhz".
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@ -35,7 +35,7 @@ public:
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}
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}
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if(isReadOperation(operation)) {
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if(is_read(operation)) {
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*value = rom_ptr_[address & 4095];
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}
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@ -28,7 +28,7 @@ public:
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if(address >= 0x1ff6 && address <= 0x1ff9) rom_ptr_ = rom_base_ + (address - 0x1ff6) * 4096;
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if(isReadOperation(operation)) {
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if(is_read(operation)) {
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*value = rom_ptr_[address & 4095];
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}
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}
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@ -53,12 +53,12 @@ public:
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if(address >= 0x1ff6 && address <= 0x1ff9) rom_ptr_ = rom_base_ + (address - 0x1ff6) * 4096;
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if(isReadOperation(operation)) {
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if(is_read(operation)) {
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*value = rom_ptr_[address & 4095];
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}
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if(address < 0x1080) ram_[address & 0x7f] = *value;
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else if(address < 0x1100 && isReadOperation(operation)) *value = ram_[address & 0x7f];
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else if(address < 0x1100 && is_read(operation)) *value = ram_[address & 0x7f];
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}
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private:
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@ -27,7 +27,7 @@ public:
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if(address >= 0x1ff4 && address <= 0x1ffb) rom_ptr_ = rom_base_ + (address - 0x1ff4) * 4096;
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if(isReadOperation(operation)) {
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if(is_read(operation)) {
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*value = rom_ptr_[address & 4095];
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}
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}
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@ -51,12 +51,12 @@ public:
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if(address >= 0x1ff4 && address <= 0x1ffb) rom_ptr_ = rom_base_ + (address - 0x1ff4) * 4096;
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if(isReadOperation(operation)) {
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if(is_read(operation)) {
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*value = rom_ptr_[address & 4095];
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}
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if(address < 0x1080) ram_[address & 0x7f] = *value;
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else if(address < 0x1100 && isReadOperation(operation)) *value = ram_[address & 0x7f];
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else if(address < 0x1100 && is_read(operation)) *value = ram_[address & 0x7f];
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}
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private:
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@ -28,7 +28,7 @@ public:
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if(address == 0x1ff8) rom_ptr_ = rom_base_;
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else if(address == 0x1ff9) rom_ptr_ = rom_base_ + 4096;
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if(isReadOperation(operation)) {
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if(is_read(operation)) {
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*value = rom_ptr_[address & 4095];
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}
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}
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@ -53,12 +53,12 @@ public:
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if(address == 0x1ff8) rom_ptr_ = rom_base_;
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if(address == 0x1ff9) rom_ptr_ = rom_base_ + 4096;
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if(isReadOperation(operation)) {
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if(is_read(operation)) {
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*value = rom_ptr_[address & 4095];
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}
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if(address < 0x1080) ram_[address & 0x7f] = *value;
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else if(address < 0x1100 && isReadOperation(operation)) *value = ram_[address & 0x7f];
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else if(address < 0x1100 && is_read(operation)) *value = ram_[address & 0x7f];
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}
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private:
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@ -27,12 +27,12 @@ public:
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if(address >= 0x1ff8 && address <= 0x1ffa) rom_ptr_ = rom_base_ + (address - 0x1ff8) * 4096;
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if(isReadOperation(operation)) {
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if(is_read(operation)) {
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*value = rom_ptr_[address & 4095];
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}
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if(address < 0x1100) ram_[address & 0xff] = *value;
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else if(address < 0x1200 && isReadOperation(operation)) *value = ram_[address & 0xff];
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else if(address < 0x1200 && is_read(operation)) *value = ram_[address & 0xff];
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}
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private:
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@ -78,13 +78,13 @@ public:
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cycles_since_6532_update_ += Cycles(cycles_run_for / 3);
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bus_extender_.advance_cycles(cycles_run_for / 3);
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if(isAccessOperation(operation)) {
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if(is_access(operation)) {
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// give the cartridge a chance to respond to the bus access
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bus_extender_.perform_bus_operation(operation, address, value);
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// check for a RIOT RAM access
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if((address&0x1280) == 0x80) {
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if(isReadOperation(operation)) {
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if(is_read(operation)) {
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returnValue &= mos6532_.get_ram(address);
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} else {
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mos6532_.set_ram(address, *value);
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@ -93,7 +93,7 @@ public:
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// check for a TIA access
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if(!(address&0x1080)) {
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if(isReadOperation(operation)) {
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if(is_read(operation)) {
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const uint16_t decodedAddress = address & 0xf;
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switch(decodedAddress) {
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case 0x00: // missile 0 / player collisions
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@ -183,14 +183,14 @@ public:
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// check for a PIA access
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if((address&0x1280) == 0x280) {
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update_6532();
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if(isReadOperation(operation)) {
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if(is_read(operation)) {
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returnValue &= mos6532_.read(address);
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} else {
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mos6532_.write(address, *value);
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}
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}
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if(isReadOperation(operation)) {
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if(is_read(operation)) {
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*value &= returnValue;
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}
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}
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@ -25,7 +25,7 @@ public:
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address &= 0x1fff;
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if(address < 0x1400) {
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if(isReadOperation(operation)) *value = ram_[address & 1023];
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if(is_read(operation)) *value = ram_[address & 1023];
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return;
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}
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@ -34,7 +34,7 @@ public:
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return;
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}
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if(isReadOperation(operation)) *value = rom_base_[address & 2047];
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if(is_read(operation)) *value = rom_base_[address & 2047];
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}
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private:
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@ -41,18 +41,18 @@ public:
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if(address < 0x1900) {
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high_ram_ptr_[address & 255] = *value;
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} else if(address < 0x1a00) {
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if(isReadOperation(operation)) *value = high_ram_ptr_[address & 255];
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if(is_read(operation)) *value = high_ram_ptr_[address & 255];
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} else {
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if(isReadOperation(operation)) *value = rom_ptr_[1][address & 2047];
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if(is_read(operation)) *value = rom_ptr_[1][address & 2047];
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}
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} else {
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if(rom_ptr_[0]) {
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if(isReadOperation(operation)) *value = rom_ptr_[0][address & 2047];
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if(is_read(operation)) *value = rom_ptr_[0][address & 2047];
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} else {
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if(address < 0x1400) {
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low_ram_[address & 1023] = *value;
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} else {
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if(isReadOperation(operation)) *value = low_ram_[address & 1023];
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if(is_read(operation)) *value = low_ram_[address & 1023];
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}
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}
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}
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@ -30,7 +30,7 @@ public:
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rom_ptr_ = rom_base_ + current_page_ * 4096;
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}
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if(isReadOperation(operation)) {
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if(is_read(operation)) {
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*value = rom_ptr_[address & 4095];
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}
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}
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@ -36,7 +36,7 @@ public:
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rom_ptr_[slot] = rom_base_ + ((address & 7) * 1024);
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}
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if(isReadOperation(operation)) {
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if(is_read(operation)) {
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*value = rom_ptr_[(address >> 10)&3][address & 1023];
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}
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}
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@ -34,7 +34,7 @@ public:
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// The random number generator
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case 0x1000: case 0x1001: case 0x1002: case 0x1003: case 0x1004:
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if(isReadOperation(operation)) {
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if(is_read(operation)) {
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*value = random_number_generator_;
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}
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random_number_generator_ = uint8_t(
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@ -85,7 +85,7 @@ public:
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// MARK: - Business as usual
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default:
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if(isReadOperation(operation)) {
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if(is_read(operation)) {
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*value = rom_ptr_[address & 4095];
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}
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break;
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@ -28,7 +28,7 @@ public:
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int offset = ((*value) * 2048) & (rom_size_ - 1);
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rom_ptr_[0] = rom_base_ + offset;
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return;
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} else if((address&0x1000) && isReadOperation(operation)) {
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} else if((address&0x1000) && is_read(operation)) {
|
||||
*value = rom_ptr_[(address >> 11)&1][address & 2047];
|
||||
}
|
||||
}
|
||||
|
@ -21,7 +21,7 @@ public:
|
||||
const uint16_t address,
|
||||
uint8_t *const value
|
||||
) {
|
||||
if(isReadOperation(operation) && (address & 0x1000)) {
|
||||
if(is_read(operation) && (address & 0x1000)) {
|
||||
*value = rom_base_[address & (rom_size_ - 1)];
|
||||
}
|
||||
}
|
||||
|
@ -76,21 +76,21 @@ Cycles MachineBase::perform_bus_operation(CPU::MOS6502::BusOperation operation,
|
||||
0xc000-0xffff ROM
|
||||
*/
|
||||
if(address < 0x800) {
|
||||
if(isReadOperation(operation))
|
||||
if(is_read(operation))
|
||||
*value = ram_[address];
|
||||
else
|
||||
ram_[address] = *value;
|
||||
} else if(address >= 0xc000) {
|
||||
if(isReadOperation(operation)) {
|
||||
if(is_read(operation)) {
|
||||
*value = rom_[address & 0x3fff];
|
||||
}
|
||||
} else if(address >= 0x1800 && address <= 0x180f) {
|
||||
if(isReadOperation(operation))
|
||||
if(is_read(operation))
|
||||
*value = serial_port_VIA_.read(address);
|
||||
else
|
||||
serial_port_VIA_.write(address, *value);
|
||||
} else if(address >= 0x1c00 && address <= 0x1c0f) {
|
||||
if(isReadOperation(operation))
|
||||
if(is_read(operation))
|
||||
*value = drive_VIA_.read(address);
|
||||
else
|
||||
drive_VIA_.write(address, *value);
|
||||
|
@ -231,7 +231,7 @@ public:
|
||||
// b1 = serial clock out and cassette write;
|
||||
// b0 = serial data out.
|
||||
|
||||
if(isReadOperation(operation)) {
|
||||
if(is_read(operation)) {
|
||||
if(!address) {
|
||||
*value = io_direction_;
|
||||
} else {
|
||||
@ -257,14 +257,14 @@ public:
|
||||
serial_port_.set_output(Serial::Line::Attention, Serial::LineLevel(~output & 0x04));
|
||||
}
|
||||
} else if(address < 0xfd00 || address >= 0xff40) {
|
||||
if(isReadOperation(operation)) {
|
||||
if(is_read(operation)) {
|
||||
*value = map_.read(address);
|
||||
} else {
|
||||
map_.write(address) = *value;
|
||||
}
|
||||
} else if(address < 0xff00) {
|
||||
// Miscellaneous hardware. All TODO.
|
||||
if(isReadOperation(operation)) {
|
||||
if(is_read(operation)) {
|
||||
// printf("TODO: read @ %04x\n", address);
|
||||
if((address & 0xfff0) == 0xfd10) {
|
||||
// 6529 parallel port, about which I know only what I've found in kernel ROM disassemblies.
|
||||
@ -295,7 +295,7 @@ public:
|
||||
// printf("TODO: write of %02x @ %04x\n", *value, address);
|
||||
}
|
||||
} else {
|
||||
if(isReadOperation(operation)) {
|
||||
if(is_read(operation)) {
|
||||
switch(address) {
|
||||
case 0xff00: *value = timers_.read<0>(); break;
|
||||
case 0xff01: *value = timers_.read<1>(); break;
|
||||
|
@ -504,7 +504,7 @@ public:
|
||||
cycles_since_mos6560_update_++;
|
||||
|
||||
// run the phase-2 part of the cycle, which is whatever the 6502 said it should be
|
||||
if(isReadOperation(operation)) {
|
||||
if(is_read(operation)) {
|
||||
uint8_t result = processor_read_memory_map_[address >> 10] ? processor_read_memory_map_[address >> 10][address & 0x3ff] : 0xff;
|
||||
if((address&0xfc00) == 0x9000) {
|
||||
if(!(address&0x100)) {
|
||||
|
@ -460,7 +460,7 @@ template <Analyser::Static::Oric::Target::DiskInterface disk_interface, CPU::MOS
|
||||
// to satisfy CPU::MOS6502::BusHandler
|
||||
forceinline Cycles perform_bus_operation(CPU::MOS6502::BusOperation operation, uint16_t address, uint8_t *value) {
|
||||
if(address > ram_top_) {
|
||||
if(!isWriteOperation(operation)) *value = paged_rom_[address - ram_top_ - 1];
|
||||
if(!is_write(operation)) *value = paged_rom_[address - ram_top_ - 1];
|
||||
|
||||
// 024D = 0 => fast; otherwise slow
|
||||
// E6C9 = read byte: return byte in A
|
||||
@ -479,39 +479,39 @@ template <Analyser::Static::Oric::Target::DiskInterface disk_interface, CPU::MOS
|
||||
} else {
|
||||
if((address & 0xff00) == 0x0300) {
|
||||
if(address < 0x0310 || (disk_interface == DiskInterface::None)) {
|
||||
if(!isWriteOperation(operation)) *value = via_.read(address);
|
||||
if(!is_write(operation)) *value = via_.read(address);
|
||||
else via_.write(address, *value);
|
||||
} else {
|
||||
switch(disk_interface) {
|
||||
default: break;
|
||||
case DiskInterface::BD500:
|
||||
if(!isWriteOperation(operation)) *value = bd500_.read(address);
|
||||
if(!is_write(operation)) *value = bd500_.read(address);
|
||||
else bd500_.write(address, *value);
|
||||
break;
|
||||
case DiskInterface::Jasmin:
|
||||
if(address >= 0x3f4) {
|
||||
if(!isWriteOperation(operation)) *value = jasmin_.read(address);
|
||||
if(!is_write(operation)) *value = jasmin_.read(address);
|
||||
else jasmin_.write(address, *value);
|
||||
}
|
||||
break;
|
||||
case DiskInterface::Microdisc:
|
||||
switch(address) {
|
||||
case 0x0310: case 0x0311: case 0x0312: case 0x0313:
|
||||
if(!isWriteOperation(operation)) *value = microdisc_.read(address);
|
||||
if(!is_write(operation)) *value = microdisc_.read(address);
|
||||
else microdisc_.write(address, *value);
|
||||
break;
|
||||
case 0x314: case 0x315: case 0x316: case 0x317:
|
||||
if(!isWriteOperation(operation)) *value = microdisc_.get_interrupt_request_register();
|
||||
if(!is_write(operation)) *value = microdisc_.get_interrupt_request_register();
|
||||
else microdisc_.set_control_register(*value);
|
||||
break;
|
||||
case 0x318: case 0x319: case 0x31a: case 0x31b:
|
||||
if(!isWriteOperation(operation)) *value = microdisc_.get_data_request_register();
|
||||
if(!is_write(operation)) *value = microdisc_.get_data_request_register();
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case DiskInterface::Pravetz:
|
||||
if(address >= 0x0320) {
|
||||
if(!isWriteOperation(operation)) *value = pravetz_rom_[pravetz_rom_base_pointer_ + (address & 0xff)];
|
||||
if(!is_write(operation)) *value = pravetz_rom_[pravetz_rom_base_pointer_ + (address & 0xff)];
|
||||
else {
|
||||
switch(address) {
|
||||
case 0x380: case 0x381: case 0x382: case 0x383:
|
||||
@ -522,13 +522,13 @@ template <Analyser::Static::Oric::Target::DiskInterface disk_interface, CPU::MOS
|
||||
}
|
||||
} else {
|
||||
const int disk_value = diskii_->read_address(address);
|
||||
if(!isWriteOperation(operation) && disk_value != Apple::DiskII::DidNotLoad) *value = uint8_t(disk_value);
|
||||
if(!is_write(operation) && disk_value != Apple::DiskII::DidNotLoad) *value = uint8_t(disk_value);
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
} else {
|
||||
if(!isWriteOperation(operation))
|
||||
if(!is_write(operation))
|
||||
*value = ram_[address];
|
||||
else {
|
||||
if(address >= 0x9800 && address <= 0xc000) video_.flush();
|
||||
|
@ -47,7 +47,7 @@ public:
|
||||
cia2_.run_for(HalfCycles(2));
|
||||
}
|
||||
|
||||
if(isAccessOperation(operation)) {
|
||||
if(is_access(operation)) {
|
||||
if(operation == BusOperation::ReadOpcode) {
|
||||
if constexpr (LogProgramCounter) {
|
||||
printf("[%04x] %02x a:%04x x:%04x y:%04x p:%02x s:%02x\n", address, memory_[address],
|
||||
|
@ -780,7 +780,7 @@ void Processor<personality, T, uses_ready_line>::run_for(const Cycles cycles) {
|
||||
if(has_stpwai(personality) && (stop_is_active_ || wait_is_active_)) {
|
||||
break;
|
||||
}
|
||||
if(uses_ready_line && ready_line_is_enabled_ && (is_65c02(personality) || isReadOperation(next_bus_operation_))) {
|
||||
if(uses_ready_line && ready_line_is_enabled_ && (is_65c02(personality) || is_read(next_bus_operation_))) {
|
||||
ready_is_active_ = true;
|
||||
break;
|
||||
}
|
||||
|
@ -99,17 +99,17 @@ enum class BusOperation {
|
||||
/*!
|
||||
For a machine watching only the RWB line, evaluates to @c true if the operation should be treated as a read; @c false otherwise.
|
||||
*/
|
||||
constexpr bool isReadOperation(BusOperation op) { return op <= BusOperation::InternalOperationRead; }
|
||||
constexpr bool is_read(BusOperation op) { return op <= BusOperation::InternalOperationRead; }
|
||||
|
||||
/*!
|
||||
For a machine watching only the RWB line, evaluates to @c true if the operation is any sort of write; @c false otherwise.
|
||||
*/
|
||||
constexpr bool isWriteOperation(BusOperation op) { return op >= BusOperation::Write; }
|
||||
constexpr bool is_write(BusOperation op) { return op >= BusOperation::Write; }
|
||||
|
||||
/*!
|
||||
Evaluates to @c true if the operation actually expects a response; @c false otherwise.
|
||||
*/
|
||||
constexpr bool isAccessOperation(BusOperation op) { return op <= BusOperation::ReadVector || op == BusOperation::Write; }
|
||||
constexpr bool is_access(BusOperation op) { return op <= BusOperation::ReadVector || op == BusOperation::Write; }
|
||||
|
||||
/*!
|
||||
A class providing empty implementations of the methods a 6502 uses to access the bus. To wire the 6502 to a bus,
|
||||
|
Loading…
x
Reference in New Issue
Block a user