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Merge pull request #1301 from TomHarte/MoreIIgsPaging
Normalise IIgs memory map interface.
This commit is contained in:
Thomas Harte
GitHub
commit
ad31c50dfd
@ -384,7 +384,7 @@ class ConcreteMachine:
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// MARK: BusHandler.
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uint64_t total = 0;
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forceinline Cycles perform_bus_operation(const CPU::WDC65816::BusOperation operation, const uint32_t address, uint8_t *const value) {
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const auto ®ion = MemoryMapRegion(memory_, address);
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const auto ®ion = memory_.region(address);
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static bool log = false;
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bool is_1Mhz = false;
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@ -945,7 +945,7 @@ class ConcreteMachine:
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is_1Mhz = region.flags & MemoryMap::Region::Is1Mhz;
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if(isReadOperation(operation)) {
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MemoryMapRead(region, address, value);
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*value = memory_.read(region, address);
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} else {
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// Shadowed writes also occur "at 1Mhz".
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// TODO: this is probably an approximation. I'm assuming that there's the ability asynchronously to post
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@ -954,7 +954,7 @@ class ConcreteMachine:
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// get by adding periodic NOPs within their copy-to-shadow step.
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//
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// Maybe the interaction with 2.8Mhz refresh isn't as straightforward as I think?
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const bool is_shadowed = IsShadowed(memory_, region, address);
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const bool is_shadowed = memory_.is_shadowed(address);
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is_1Mhz |= is_shadowed;
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// Use a very broad test for flushing video: any write to $e0 or $e1, or any write that is shadowed.
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@ -963,7 +963,7 @@ class ConcreteMachine:
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video_.flush();
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}
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MemoryMapWrite(memory_, region, address, value);
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memory_.write(region, address, *value);
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}
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}
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@ -248,13 +248,124 @@ class MemoryMap {
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uint8_t speed_register_ = 0x00;
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// MARK: - Memory banking.
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#define assert_is_region(start, end) \
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assert(region_map[start] == region_map[start-1]+1); \
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assert(region_map[end-1] == region_map[start]); \
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void assert_is_region(uint8_t start, uint8_t end) {
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assert(region_map[start] == region_map[start-1]+1);
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assert(region_map[end-1] == region_map[start]);
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assert(region_map[end] == region_map[end-1]+1);
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}
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template <int type> void set_paging() {
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// Establish whether main or auxiliary RAM
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// is exposed in bank $00 for a bunch of regions.
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if constexpr (type & PagingType::Main) {
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const auto set = [&](std::size_t page, const auto &flags) {
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auto ®ion = regions[region_map[page]];
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region.read = flags.read ? &ram_base[0x01'0000] : ram_base;
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region.write = flags.write ? &ram_base[0x01'0000] : ram_base;
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};
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const auto state = auxiliary_switches_.main_state();
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// Base: $0200–$03FF.
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set(0x02, state.base);
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assert_is_region(0x02, 0x04);
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// Region $0400–$07ff.
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set(0x04, state.region_04_08);
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assert_is_region(0x04, 0x08);
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// Base: $0800–$1FFF.
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set(0x08, state.base);
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assert_is_region(0x08, 0x20);
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// Region $2000–$3FFF.
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set(0x20, state.region_20_40);
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assert_is_region(0x20, 0x40);
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// Base: $4000–$BFFF.
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set(0x40, state.base);
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assert_is_region(0x40, 0xc0);
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}
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// Update whether base or auxiliary RAM is visible in: (i) the zero
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// and stack pages; and (ii) anywhere that the language card is exposing RAM instead of ROM.
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if constexpr (bool(type & PagingType::ZeroPage)) {
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// Affects bank $00 only, and should be a single region.
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auto ®ion = regions[region_map[0]];
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region.read = region.write = auxiliary_switches_.zero_state() ? &ram_base[0x01'0000] : ram_base;
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assert(region_map[0x0000] == region_map[0x0001]);
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assert(region_map[0x0001]+1 == region_map[0x0002]);
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}
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// Establish whether ROM or card switches are exposed in the distinct
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// regions C100–C2FF, C300–C3FF, C400–C7FF and C800–CFFF.
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//
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// On the IIgs it intersects with the current shadow register.
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if constexpr (bool(type & (PagingType::CardArea | PagingType::Main))) {
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const bool inhibit_banks0001 = shadow_register_ & 0x40;
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const auto state = auxiliary_switches_.card_state();
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auto apply = [&state, this](uint32_t bank_base) {
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auto &c0_region = regions[region_map[bank_base | 0xc0]];
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auto &c1_region = regions[region_map[bank_base | 0xc1]];
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auto &c3_region = regions[region_map[bank_base | 0xc3]];
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auto &c4_region = regions[region_map[bank_base | 0xc4]];
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auto &c8_region = regions[region_map[bank_base | 0xc8]];
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const uint8_t *const rom = ®ions[region_map[0xffd0]].read[0xffc100] - ((bank_base << 8) + 0xc100);
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// This is applied dynamically as it may be added or lost in banks $00 and $01.
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c0_region.flags |= Region::IsIO;
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const auto apply_region = [&](bool flag, auto ®ion) {
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region.write = nullptr;
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if(flag) {
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region.read = rom;
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region.flags &= ~Region::IsIO;
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} else {
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region.flags |= Region::IsIO;
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}
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};
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apply_region(state.region_C1_C3, c1_region);
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apply_region(state.region_C3, c3_region);
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apply_region(state.region_C4_C8, c4_region);
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apply_region(state.region_C8_D0, c8_region);
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// Sanity checks.
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assert(region_map[bank_base | 0xc1] == region_map[bank_base | 0xc0]+1);
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assert(region_map[bank_base | 0xc2] == region_map[bank_base | 0xc1]);
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assert(region_map[bank_base | 0xc3] == region_map[bank_base | 0xc2]+1);
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assert(region_map[bank_base | 0xc4] == region_map[bank_base | 0xc3]+1);
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assert(region_map[bank_base | 0xc7] == region_map[bank_base | 0xc4]);
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assert(region_map[bank_base | 0xc8] == region_map[bank_base | 0xc7]+1);
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assert(region_map[bank_base | 0xcf] == region_map[bank_base | 0xc8]);
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assert(region_map[bank_base | 0xd0] == region_map[bank_base | 0xcf]+1);
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};
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if(inhibit_banks0001) {
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// Set no IO in the Cx00 range for banks $00 and $01, just
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// regular RAM (or possibly auxiliary).
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const auto auxiliary_state = auxiliary_switches_.main_state();
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for(uint8_t region = region_map[0x00c0]; region < region_map[0x00d0]; region++) {
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regions[region].read = auxiliary_state.base.read ? &ram_base[0x01'0000] : ram_base;
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regions[region].write = auxiliary_state.base.write ? &ram_base[0x01'0000] : ram_base;
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regions[region].flags &= ~Region::IsIO;
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}
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for(uint8_t region = region_map[0x01c0]; region < region_map[0x01d0]; region++) {
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regions[region].read = regions[region].write = ram_base;
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regions[region].flags &= ~Region::IsIO;
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}
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} else {
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// Obey the card state for banks $00 and $01.
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apply(0x0000);
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apply(0x0100);
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}
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// Obey the card state for banks $e0 and $e1.
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apply(0xe000);
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apply(0xe100);
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}
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// Update the region from
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// $D000 onwards as per the state of the language card flags — there may
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// end up being ROM or RAM (or auxiliary RAM), and the first 4kb of it
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@ -314,121 +425,6 @@ class MemoryMap {
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apply(0xe000, e0_ram);
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apply(0xe100, e0_ram);
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}
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// Establish whether main or auxiliary RAM
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// is exposed in bank $00 for a bunch of regions.
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if constexpr (type & PagingType::Main) {
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const auto state = auxiliary_switches_.main_state();
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#define set(page, flags) {\
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auto ®ion = regions[region_map[page]]; \
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region.read = flags.read ? &ram_base[0x01'0000] : ram_base; \
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region.write = flags.write ? &ram_base[0x01'0000] : ram_base; \
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}
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// Base: $0200–$03FF.
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set(0x02, state.base);
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assert_is_region(0x02, 0x04);
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// Region $0400–$07ff.
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set(0x04, state.region_04_08);
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assert_is_region(0x04, 0x08);
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// Base: $0800–$1FFF.
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set(0x08, state.base);
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assert_is_region(0x08, 0x20);
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// Region $2000–$3FFF.
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set(0x20, state.region_20_40);
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assert_is_region(0x20, 0x40);
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// Base: $4000–$BFFF.
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set(0x40, state.base);
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assert_is_region(0x40, 0xc0);
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#undef set
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}
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// Update whether base or auxiliary RAM is visible in: (i) the zero
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// and stack pages; and (ii) anywhere that the language card is exposing RAM instead of ROM.
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if constexpr (bool(type & PagingType::ZeroPage)) {
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// Affects bank $00 only, and should be a single region.
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auto ®ion = regions[region_map[0]];
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region.read = region.write = auxiliary_switches_.zero_state() ? &ram_base[0x01'0000] : ram_base;
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assert(region_map[0x0000] == region_map[0x0001]);
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assert(region_map[0x0001]+1 == region_map[0x0002]);
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}
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// Establish whether ROM or card switches are exposed in the distinct
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// regions C100–C2FF, C300–C3FF, C400–C7FF and C800–CFFF.
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//
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// On the IIgs it intersects with the current shadow register.
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if constexpr (bool(type & (PagingType::CardArea | PagingType::Main))) {
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const bool inhibit_banks0001 = shadow_register_ & 0x40;
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const auto state = auxiliary_switches_.card_state();
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auto apply = [&state, this](uint32_t bank_base) {
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auto &c0_region = regions[region_map[bank_base | 0xc0]];
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auto &c1_region = regions[region_map[bank_base | 0xc1]];
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auto &c3_region = regions[region_map[bank_base | 0xc3]];
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auto &c4_region = regions[region_map[bank_base | 0xc4]];
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auto &c8_region = regions[region_map[bank_base | 0xc8]];
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const uint8_t *const rom = ®ions[region_map[0xffd0]].read[0xffc100] - ((bank_base << 8) + 0xc100);
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// This is applied dynamically as it may be added or lost in banks $00 and $01.
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c0_region.flags |= Region::IsIO;
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#define apply_region(flag, region) \
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region.write = nullptr; \
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if(flag) { \
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region.read = rom; \
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region.flags &= ~Region::IsIO; \
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} else { \
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region.flags |= Region::IsIO; \
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}
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apply_region(state.region_C1_C3, c1_region);
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apply_region(state.region_C3, c3_region);
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apply_region(state.region_C4_C8, c4_region);
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apply_region(state.region_C8_D0, c8_region);
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#undef apply_region
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// Sanity checks.
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assert(region_map[bank_base | 0xc1] == region_map[bank_base | 0xc0]+1);
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assert(region_map[bank_base | 0xc2] == region_map[bank_base | 0xc1]);
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assert(region_map[bank_base | 0xc3] == region_map[bank_base | 0xc2]+1);
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assert(region_map[bank_base | 0xc4] == region_map[bank_base | 0xc3]+1);
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assert(region_map[bank_base | 0xc7] == region_map[bank_base | 0xc4]);
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assert(region_map[bank_base | 0xc8] == region_map[bank_base | 0xc7]+1);
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assert(region_map[bank_base | 0xcf] == region_map[bank_base | 0xc8]);
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assert(region_map[bank_base | 0xd0] == region_map[bank_base | 0xcf]+1);
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};
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if(inhibit_banks0001) {
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// Set no IO in the Cx00 range for banks $00 and $01, just
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// regular RAM (or possibly auxiliary).
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const auto auxiliary_state = auxiliary_switches_.main_state();
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for(uint8_t region = region_map[0x00c0]; region < region_map[0x00d0]; region++) {
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regions[region].read = auxiliary_state.base.read ? &ram_base[0x01'0000] : ram_base;
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regions[region].write = auxiliary_state.base.write ? &ram_base[0x01'0000] : ram_base;
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regions[region].flags &= ~Region::IsIO;
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}
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for(uint8_t region = region_map[0x01c0]; region < region_map[0x01d0]; region++) {
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regions[region].read = regions[region].write = ram_base;
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regions[region].flags &= ~Region::IsIO;
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}
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} else {
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// Obey the card state for banks $00 and $01.
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apply(0x0000);
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apply(0x0100);
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}
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// Obey the card state for banks $e0 and $e1.
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apply(0xe000);
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apply(0xe100);
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}
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}
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// IIgs specific: sets or resets the ::IsShadowed flag across affected banks as
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@ -563,8 +559,6 @@ class MemoryMap {
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}
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}
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#undef assert_is_region
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private:
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// Various precomputed bitsets describing key regions; std::bitset doesn't support constexpr instantiation
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// beyond the first 64 bits at the time of writing, alas, so these are generated at runtime.
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@ -637,54 +631,48 @@ class MemoryMap {
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std::array<Region, 40> regions; // An assert above ensures that this is large enough; there's no
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// doctrinal reason for it to be whatever size it is now, just
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// adjust as required.
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};
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// TODO: branching below on region.read/write is predicated on the idea that extra scratch space
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// would be less efficient. Verify that?
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// The below encapsulates an assumption that Apple intends to shadow physical addresses (i.e. after mapping).
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// If the Apple shadows logical addresses (i.e. prior to mapping) then see commented out alternatives.
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#define MemoryMapRegion(map, address) map.regions[map.region_map[address >> 8]]
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#define MemoryMapRead(region, address, value) *value = region.read ? region.read[address] : 0xff
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// The below encapsulates the fact that I've yet to determine whether Apple intends to
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// indicate that logical addresses (i.e. those prior to being mapped per the current paging)
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// or physical addresses (i.e. after mapping) are subject to shadowing.
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#ifdef SHADOW_LOGICAL
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#define IsShadowed(map, region, address) \
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(map.shadow_pages[((®ion.write[address] - map.ram_base) >> 10) & 127] & map.shadow_banks[address >> 17])
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#define MemoryMapWrite(map, region, address, value) \
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if(region.write) { \
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region.write[address] = *value; \
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const bool _mm_is_shadowed = IsShadowed(map, region, address); \
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map.shadow_base[_mm_is_shadowed][address & map.shadow_mask[_mm_is_shadowed]] = *value; \
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const Region ®ion(uint32_t address) { return regions[region_map[address >> 8]]; }
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uint8_t read(const Region ®ion, uint32_t address) {
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return region.read ? region.read[address] : 0xff;
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}
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#else
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bool is_shadowed(uint32_t address) const {
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// Logical mapping alternative:
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// shadow_pages[((®ion.write[address] - ram_base) >> 10) & 127] & shadow_banks[address >> 17]
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#define IsShadowed(map, region, address) \
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(map.shadow_pages[(address >> 10) & 127] & map.shadow_banks[address >> 17])
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return shadow_pages[(address >> 10) & 127] & shadow_banks[address >> 17];
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#define MemoryMapWrite(map, region, address, value) \
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if(region.write) { \
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region.write[address] = *value; \
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const bool _mm_is_shadowed = IsShadowed(map, region, address); \
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map.shadow_base[_mm_is_shadowed][(®ion.write[address] - map.ram_base) & map.shadow_mask[_mm_is_shadowed]] = *value; \
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}
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#endif
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// Quick notes on ::IsShadowed contortions:
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// Quick notes on contortions above:
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//
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// The objective is to support shadowing:
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// 1. without storing a whole extra pointer, and such that the shadowing flags are orthogonal to the current auxiliary memory settings;
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// 1. without storing a whole extra pointer, and such that the shadowing flags
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// are orthogonal to the current auxiliary memory settings;
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// 2. in such a way as to support shadowing both in banks $00/$01 and elsewhere; and
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// 3. to do so without introducing too much in the way of branching.
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//
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// Hence the implemented solution: if shadowing is enabled then use the distance from the start of physical RAM
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// modulo 128k indexed into the bank $e0/$e1 RAM.
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// Hence the implemented solution: if shadowing is enabled then use the distance from the start of
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// physical RAM modulo 128k indexed into the bank $e0/$e1 RAM.
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//
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// With a further twist: the modulo and pointer are indexed on ::IsShadowed to eliminate a branch even on that.
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// With a further twist: the modulo and pointer are indexed on ::IsShadowed to eliminate a branch
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// even on that.
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}
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void write(const Region ®ion, uint32_t address, uint8_t value) {
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if(!region.write) {
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return;
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}
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region.write[address] = value;
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const bool shadowed = is_shadowed(address);
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shadow_base[shadowed][(®ion.write[address] - ram_base) & shadow_mask[shadowed]] = value;
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// Logical mapping alternative:
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// shadow_base[shadowed][address & shadow_mask[shadowed]]
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}
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};
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}
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@ -535,7 +535,6 @@
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4B8334861F5DA3780097E338 /* 6502Storage.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 4B8334851F5DA3780097E338 /* 6502Storage.cpp */; };
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4B83348A1F5DB94B0097E338 /* IRQDelegatePortHandler.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 4B8334891F5DB94B0097E338 /* IRQDelegatePortHandler.cpp */; };
|
||||
4B8334951F5E25B60097E338 /* C1540.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 4B8334941F5E25B60097E338 /* C1540.cpp */; };
|
||||
4B85322D227793CB00F26553 /* etos192uk.trace.txt.gz in Resources */ = {isa = PBXBuildFile; fileRef = 4B85322C227793CA00F26553 /* etos192uk.trace.txt.gz */; };
|
||||
4B85322F2277ABDE00F26553 /* tos100.trace.txt.gz in Resources */ = {isa = PBXBuildFile; fileRef = 4B85322E2277ABDD00F26553 /* tos100.trace.txt.gz */; };
|
||||
4B86E25B1F8C628F006FAA45 /* Keyboard.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 4B86E2591F8C628F006FAA45 /* Keyboard.cpp */; };
|
||||
4B8805F01DCFC99C003085B1 /* Acorn.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 4B8805EE1DCFC99C003085B1 /* Acorn.cpp */; };
|
||||
@ -1622,7 +1621,6 @@
|
||||
4B8334911F5E24FF0097E338 /* C1540Base.hpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.h; name = C1540Base.hpp; path = Implementation/C1540Base.hpp; sourceTree = "<group>"; };
|
||||
4B8334941F5E25B60097E338 /* C1540.cpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.cpp; name = C1540.cpp; path = Implementation/C1540.cpp; sourceTree = "<group>"; };
|
||||
4B85322922778E4200F26553 /* Comparative68000.hpp */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.h; path = Comparative68000.hpp; sourceTree = "<group>"; };
|
||||
4B85322C227793CA00F26553 /* etos192uk.trace.txt.gz */ = {isa = PBXFileReference; lastKnownFileType = archive.gzip; path = etos192uk.trace.txt.gz; sourceTree = "<group>"; };
|
||||
4B85322E2277ABDD00F26553 /* tos100.trace.txt.gz */ = {isa = PBXFileReference; lastKnownFileType = archive.gzip; path = tos100.trace.txt.gz; sourceTree = "<group>"; };
|
||||
4B86E2591F8C628F006FAA45 /* Keyboard.cpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.cpp; path = Keyboard.cpp; sourceTree = "<group>"; };
|
||||
4B86E25A1F8C628F006FAA45 /* Keyboard.hpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.h; path = Keyboard.hpp; sourceTree = "<group>"; };
|
||||
@ -3540,7 +3538,6 @@
|
||||
isa = PBXGroup;
|
||||
children = (
|
||||
4B85322E2277ABDD00F26553 /* tos100.trace.txt.gz */,
|
||||
4B85322C227793CA00F26553 /* etos192uk.trace.txt.gz */,
|
||||
);
|
||||
path = "TOS Startup";
|
||||
sourceTree = "<group>";
|
||||
@ -5411,7 +5408,6 @@
|
||||
4BB298FB1B587D8400A49093 /* ancb in Resources */,
|
||||
4BB299431B587D8400A49093 /* dcma in Resources */,
|
||||
4BB298FD1B587D8400A49093 /* andax in Resources */,
|
||||
4B85322D227793CB00F26553 /* etos192uk.trace.txt.gz in Resources */,
|
||||
4B8DF6262550D91600F3433C /* CPUEOR-trace_compare.log in Resources */,
|
||||
4BB299401B587D8400A49093 /* cpya in Resources */,
|
||||
4BB299BE1B587D8400A49093 /* rraix in Resources */,
|
||||
|
||||
@ -36,7 +36,7 @@ class EmuTOS: public ComparativeBusHandler {
|
||||
return m68000_.get_state();
|
||||
}
|
||||
|
||||
template <typename Microcycle> perform_bus_operation(const Microcycle &cycle, int) {
|
||||
template <typename Microcycle> HalfCycles perform_bus_operation(const Microcycle &cycle, int) {
|
||||
const uint32_t address = cycle.word_address();
|
||||
uint32_t word_address = address;
|
||||
|
||||
@ -56,7 +56,6 @@ class EmuTOS: public ComparativeBusHandler {
|
||||
word_address %= ram_.size();
|
||||
}
|
||||
|
||||
using Microcycle = CPU::MC68000::Microcycle;
|
||||
if(cycle.data_select_active()) {
|
||||
uint16_t peripheral_result = 0xffff;
|
||||
if(is_peripheral) {
|
||||
@ -68,20 +67,20 @@ class EmuTOS: public ComparativeBusHandler {
|
||||
}
|
||||
}
|
||||
|
||||
const auto operation = (op != Microcycle::DecodeDynamically) ? op : cycle.operation;
|
||||
switch(operation & (Microcycle::SelectWord | Microcycle::SelectByte | Microcycle::Read)) {
|
||||
using namespace CPU::MC68000;
|
||||
switch(cycle.operation & (Operation::SelectWord | Operation::SelectByte | Operation::Read)) {
|
||||
default: break;
|
||||
|
||||
case Microcycle::SelectWord | Microcycle::Read:
|
||||
case Operation::SelectWord | Operation::Read:
|
||||
cycle.value->w = is_peripheral ? peripheral_result : base[word_address];
|
||||
break;
|
||||
case Microcycle::SelectByte | Microcycle::Read:
|
||||
case Operation::SelectByte | Operation::Read:
|
||||
cycle.value->b = (is_peripheral ? peripheral_result : base[word_address]) >> cycle.byte_shift();
|
||||
break;
|
||||
case Microcycle::SelectWord:
|
||||
case Operation::SelectWord:
|
||||
base[word_address] = cycle.value->w;
|
||||
break;
|
||||
case Microcycle::SelectByte:
|
||||
case Operation::SelectByte:
|
||||
base[word_address] = (cycle.value->b << cycle.byte_shift()) | (base[word_address] & (0xffff ^ cycle.byte_mask()));
|
||||
break;
|
||||
}
|
||||
|
||||
@ -38,16 +38,14 @@ namespace {
|
||||
}
|
||||
|
||||
- (void)write:(uint8_t)value address:(uint32_t)address {
|
||||
const auto ®ion = MemoryMapRegion(_memoryMap, address);
|
||||
const auto ®ion = _memoryMap.region(address);
|
||||
XCTAssertFalse(region.flags & MemoryMap::Region::IsIO);
|
||||
MemoryMapWrite(_memoryMap, region, address, &value);
|
||||
_memoryMap.write(region, address, value);
|
||||
}
|
||||
|
||||
- (uint8_t)readAddress:(uint32_t)address {
|
||||
const auto ®ion = MemoryMapRegion(_memoryMap, address);
|
||||
uint8_t value;
|
||||
MemoryMapRead(region, address, &value);
|
||||
return value;
|
||||
const auto ®ion = _memoryMap.region(address);
|
||||
return _memoryMap.read(region, address);
|
||||
}
|
||||
|
||||
- (void)testAllRAM {
|
||||
@ -371,8 +369,7 @@ namespace {
|
||||
while(logical < [next intValue]) {
|
||||
[[maybe_unused]] const auto ®ion =
|
||||
self->_memoryMap.regions[self->_memoryMap.region_map[logical]];
|
||||
const bool isShadowed =
|
||||
IsShadowed(_memoryMap, region, (logical << 8));
|
||||
const bool isShadowed = _memoryMap.is_shadowed(logical << 8);
|
||||
|
||||
XCTAssertEqual(
|
||||
isShadowed,
|
||||
|
||||
@ -59,20 +59,21 @@ class QL: public ComparativeBusHandler {
|
||||
if(cycle.data_select_active()) {
|
||||
uint16_t peripheral_result = 0xffff;
|
||||
|
||||
switch(cycle.operation & (Microcycle::SelectWord | Microcycle::SelectByte | Microcycle::Read)) {
|
||||
using namespace CPU::MC68000;
|
||||
switch(cycle.operation & (Operation::SelectWord | Operation::SelectByte | Operation::Read)) {
|
||||
default: break;
|
||||
|
||||
case Microcycle::SelectWord | Microcycle::Read:
|
||||
case Operation::SelectWord | Operation::Read:
|
||||
cycle.value->w = is_peripheral ? peripheral_result : base[word_address];
|
||||
break;
|
||||
case Microcycle::SelectByte | Microcycle::Read:
|
||||
case Operation::SelectByte | Operation::Read:
|
||||
cycle.value->b = (is_peripheral ? peripheral_result : base[word_address]) >> cycle.byte_shift();
|
||||
break;
|
||||
case Microcycle::SelectWord:
|
||||
case Operation::SelectWord:
|
||||
assert(!(is_rom && !is_peripheral));
|
||||
if(!is_peripheral) base[word_address] = cycle.value->w;
|
||||
break;
|
||||
case Microcycle::SelectByte:
|
||||
case Operation::SelectByte:
|
||||
assert(!(is_rom && !is_peripheral));
|
||||
if(!is_peripheral) base[word_address] = (cycle.value->b << cycle.byte_shift()) | (base[word_address] & (0xffff ^ cycle.byte_mask()));
|
||||
break;
|
||||
|
||||
@ -82,24 +82,23 @@ class RAM68000: public CPU::MC68000::BusHandler {
|
||||
const uint32_t word_address = cycle.word_address();
|
||||
duration_ += cycle.length;
|
||||
|
||||
const auto operation = (op != Microcycle::DecodeDynamically) ? op : cycle.operation;
|
||||
if(cycle.data_select_active()) {
|
||||
if(operation & Microcycle::InterruptAcknowledge) {
|
||||
if(cycle.operation & CPU::MC68000::Operation::InterruptAcknowledge) {
|
||||
cycle.value->b = 10;
|
||||
} else {
|
||||
switch(operation & (Microcycle::SelectWord | Microcycle::SelectByte | Microcycle::Read)) {
|
||||
switch(cycle.operation & (CPU::MC68000::Operation::SelectWord | CPU::MC68000::Operation::SelectByte | CPU::MC68000::Operation::Read)) {
|
||||
default: break;
|
||||
|
||||
case Microcycle::SelectWord | Microcycle::Read:
|
||||
case CPU::MC68000::Operation::SelectWord | CPU::MC68000::Operation::Read:
|
||||
cycle.value->w = ram_[word_address % ram_.size()];
|
||||
break;
|
||||
case Microcycle::SelectByte | Microcycle::Read:
|
||||
case CPU::MC68000::Operation::SelectByte | CPU::MC68000::Operation::Read:
|
||||
cycle.value->b = ram_[word_address % ram_.size()] >> cycle.byte_shift();
|
||||
break;
|
||||
case Microcycle::SelectWord:
|
||||
case CPU::MC68000::Operation::SelectWord:
|
||||
ram_[word_address % ram_.size()] = cycle.value->w;
|
||||
break;
|
||||
case Microcycle::SelectByte:
|
||||
case CPU::MC68000::Operation::SelectByte:
|
||||
ram_[word_address % ram_.size()] = uint16_t(
|
||||
(cycle.value->b << cycle.byte_shift()) |
|
||||
(ram_[word_address % ram_.size()] & cycle.untouched_byte_mask())
|
||||
|
||||
Loading…
Reference in New Issue
Block a user