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https://github.com/TomHarte/CLK.git
synced 2024-11-25 16:31:42 +00:00
Add a 2Mhz tick for timers.
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@ -151,6 +151,38 @@ struct Video {
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};
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struct Interrupts {
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// TODO: timers, which decrement at 2Mhz.
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void tick_timers() {
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}
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bool read(uint32_t address, uint8_t &value) {
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switch(address & 0x7f) {
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default: break;
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case 0x10: // IRQ status A
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value = irq_status_a();
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return true;
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case 0x20: // IRQ status B
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value = 0x00;
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return true;
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case 0x30: // FIQ status
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value = 0x80;
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return true;
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}
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logger.error().append("TODO: IO controller read from %08x", address);
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return false;
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}
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bool write(uint32_t address, uint8_t value) {
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logger.error().append("TODO: IO controller write of %02x at %08x", value, address);
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return false;
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}
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private:
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uint8_t irq_status_a() const {
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return irq_status_a_;
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}
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@ -210,9 +242,7 @@ struct Memory {
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return true;
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} break;
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case Zone::IOControllers:
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logger.error().append("TODO: Write to IO controllers of %08x to %08x", source, address);
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break;
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case Zone::IOControllers: return ioc_.write(address, source);
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case Zone::VideoController:
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// TODO: handle byte writes correctly.
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@ -273,24 +303,19 @@ struct Memory {
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source = high_rom<IntT>(address);
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return true;
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case Zone::IOControllers:
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switch(address & 0x7f) {
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default: break;
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case 0x10: // IRQ status A
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source = ioc_.irq_status_a();
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return true;
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case 0x20: // IRQ status B
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source = 0x00;
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return true;
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case 0x30: // FIQ status
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source = 0x80;
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case Zone::IOControllers: {
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if constexpr (std::is_same_v<IntT, uint8_t>) {
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return ioc_.read(address, source);
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} else {
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// TODO: generalise this adaptation of an 8-bit device to the 32-bit bus, which probably isn't right anyway.
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uint8_t value;
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if(!ioc_.read(address, value)) {
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return false;
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}
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source = value;
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return true;
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}
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logger.error().append("TODO: IO controller read from %08x", address);
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break;
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}
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default:
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logger.error().append("TODO: read from %08x", address);
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@ -306,6 +331,10 @@ struct Memory {
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update_mapping();
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}
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void tick_timers() {
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ioc_.tick_timers();
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}
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private:
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bool has_moved_rom_ = false;
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std::array<uint8_t, 4*1024*1024> ram_{};
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@ -522,11 +551,20 @@ class ConcreteMachine:
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public MachineTypes::TimedMachine,
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public MachineTypes::ScanProducer
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{
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// TODO: pick a sensible clock rate; this is just code for '20 MIPS, please'.
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static constexpr int ClockRate = 20'000'000;
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// Timers tick at 2Mhz, so figure out the proper divider for that.
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static constexpr int TimerTarget = ClockRate / 2'000'000;
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int timer_divider_ = TimerTarget;
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public:
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ConcreteMachine(
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const Analyser::Static::Target &target,
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const ROMMachine::ROMFetcher &rom_fetcher
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) {
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set_clock_rate(ClockRate);
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constexpr ROM::Name risc_os = ROM::Name::AcornRISCOS319;
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ROM::Request request(risc_os);
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auto roms = rom_fetcher(request);
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@ -535,10 +573,6 @@ class ConcreteMachine:
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}
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executor_.bus.set_rom(roms.find(risc_os)->second);
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// TODO: pick a sensible clock rate; this is just code for '20 MIPS, please'.
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set_clock_rate(20'000'000);
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insert_media(target.media);
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}
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@ -557,7 +591,13 @@ class ConcreteMachine:
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static uint32_t last_pc = 0;
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auto instructions = cycles.as<int>();
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while(instructions--) {
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while(instructions) {
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auto run_length = std::min(timer_divider_, instructions);
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instructions -= run_length;
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timer_divider_ -= run_length;
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while(run_length--) {
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uint32_t instruction;
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if(!executor_.bus.read(executor_.pc(), instruction, executor_.registers().mode(), false)) {
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logger.info().append("Prefetch abort at %08x; last good was at %08x", executor_.pc(), last_pc);
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@ -576,6 +616,14 @@ class ConcreteMachine:
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// }
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InstructionSet::ARM::execute<arm_model>(instruction, executor_);
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}
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if(!timer_divider_) {
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executor_.bus.tick_timers();
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timer_divider_ = TimerTarget;
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}
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}
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}
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// MARK: - MediaTarget
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