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Decode PIT mode writes.
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2b69081fff
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@ -20,6 +20,7 @@
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namespace PCCompatible {
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namespace PCCompatible {
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template <bool is_8254>
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class PIT {
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class PIT {
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public:
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public:
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template <int channel> uint8_t read() {
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template <int channel> uint8_t read() {
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@ -29,16 +30,58 @@ class PIT {
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template <int channel> void write([[maybe_unused]] uint8_t value) {
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template <int channel> void write([[maybe_unused]] uint8_t value) {
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}
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}
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void set_mode([[maybe_unused]] uint8_t value) {
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void set_mode(uint8_t value) {
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const int channel = (value >> 6) & 3;
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const int channel_id = (value >> 6) & 3;
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if(channel == 3) {
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if(channel_id == 3) {
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read_back_ = is_8254;
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return;
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return;
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}
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}
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Channel &channel = channels_[channel_id];
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channel.is_bcd = value & 1;
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switch((value >> 1) & 3) {
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default: channel.latch_value(); break;
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case 1: channel.latch_mode = LatchMode::LowOnly; break;
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case 2: channel.latch_mode = LatchMode::HighOnly; break;
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case 3: channel.latch_mode = LatchMode::LowHigh; break;
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}
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const auto operating_mode = (value >> 3) & 7;
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switch(operating_mode) {
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default: channel.mode = OperatingMode(operating_mode); break;
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case 6: channel.mode = OperatingMode::RateGenerator; break;
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case 7: channel.mode = OperatingMode::SquareWaveGenerator; break;
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}
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}
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}
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private:
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private:
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// Supported only on 8254s.
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bool read_back_ = false;
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enum class LatchMode {
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enum class LatchMode {
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LowOnly,
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HighOnly,
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LowHigh,
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};
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};
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enum class OperatingMode {
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InterruptOnTerminalCount = 0,
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HardwareRetriggerableOneShot = 1,
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RateGenerator = 2,
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SquareWaveGenerator = 3,
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SoftwareTriggeredStrobe = 4,
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HardwareTriggeredStrobe = 5,
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};
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struct Channel {
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LatchMode latch_mode = LatchMode::LowHigh;
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OperatingMode mode = OperatingMode::InterruptOnTerminalCount;
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bool is_bcd = false;
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void latch_value() {}
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} channels_[3];
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};
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};
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struct Registers {
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struct Registers {
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