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Corrects a counting error in the MSX.
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@ -282,13 +282,6 @@ class ConcreteMachine:
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// MARK: Z80::BusHandler
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// MARK: Z80::BusHandler
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forceinline HalfCycles perform_machine_cycle(const CPU::Z80::PartialMachineCycle &cycle) {
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forceinline HalfCycles perform_machine_cycle(const CPU::Z80::PartialMachineCycle &cycle) {
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if(time_until_interrupt_ > 0) {
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time_until_interrupt_ -= cycle.length;
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if(time_until_interrupt_ <= HalfCycles(0)) {
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z80_.set_interrupt_line(true, time_until_interrupt_);
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}
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}
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uint16_t address = cycle.address ? *cycle.address : 0x0000;
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uint16_t address = cycle.address ? *cycle.address : 0x0000;
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switch(cycle.operation) {
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switch(cycle.operation) {
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case CPU::Z80::PartialMachineCycle::ReadOpcode:
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case CPU::Z80::PartialMachineCycle::ReadOpcode:
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@ -468,13 +461,21 @@ class ConcreteMachine:
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// Per the best information I currently have, the MSX inserts an extra cycle into each opcode read,
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// Per the best information I currently have, the MSX inserts an extra cycle into each opcode read,
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// but otherwise runs without pause.
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// but otherwise runs without pause.
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HalfCycles addition((cycle.operation == CPU::Z80::PartialMachineCycle::ReadOpcode) ? 2 : 0);
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const HalfCycles addition((cycle.operation == CPU::Z80::PartialMachineCycle::ReadOpcode) ? 2 : 0);
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time_since_vdp_update_ += cycle.length + addition;
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const HalfCycles total_length = addition + cycle.length;
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time_since_ay_update_ += cycle.length + addition;
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memory_slots_[0].cycles_since_update += cycle.length + addition;
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if(time_until_interrupt_ > 0) {
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memory_slots_[1].cycles_since_update += cycle.length + addition;
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time_until_interrupt_ -= total_length;
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memory_slots_[2].cycles_since_update += cycle.length + addition;
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if(time_until_interrupt_ <= HalfCycles(0)) {
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memory_slots_[3].cycles_since_update += cycle.length + addition;
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z80_.set_interrupt_line(true, time_until_interrupt_);
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}
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}
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time_since_vdp_update_ += total_length;
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time_since_ay_update_ += total_length;
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memory_slots_[0].cycles_since_update += total_length;
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memory_slots_[1].cycles_since_update += total_length;
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memory_slots_[2].cycles_since_update += total_length;
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memory_slots_[3].cycles_since_update += total_length;
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return addition;
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return addition;
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}
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}
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