From b1616be4b82a9bb06d125eb38779f0ce78d383f1 Mon Sep 17 00:00:00 2001 From: Thomas Harte Date: Sat, 17 Jul 2021 21:36:20 -0400 Subject: [PATCH] Gets to what is probably a CIA access? --- Machines/Amiga/Amiga.cpp | 28 ++++++++++++++++++++++++---- 1 file changed, 24 insertions(+), 4 deletions(-) diff --git a/Machines/Amiga/Amiga.cpp b/Machines/Amiga/Amiga.cpp index 863f49ef8..34f27198a 100644 --- a/Machines/Amiga/Amiga.cpp +++ b/Machines/Amiga/Amiga.cpp @@ -79,11 +79,31 @@ class ConcreteMachine: // Grab the target address to pick a memory source. const uint32_t address = cycle.host_endian_byte_address(); - if(!regions_[address >> 18].read_write_mask) { - // TODO: registers, etc, here. - assert(false); + if(cycle.operation & (Microcycle::SelectByte | Microcycle::SelectWord)) { + printf("%06x\n", address); + } + + if(!regions_[address >> 18].read_write_mask) { + if((cycle.operation & (Microcycle::SelectByte | Microcycle::SelectWord))) { + // Check for various potential chip accesses. + if(address >= 0xbf'd000 && address <= 0xbf'ef01) { + printf("Unimplemented CIA %06x\n", address); + assert(false); + } else if(address >= 0xdf'f000 && address <= 0xdf'f1be) { + printf("Unimplemented chipset access %06x\n", address); + assert(false); + } else { + // This'll do for open bus, for now. + cycle.set_value16(0xffff); + } + } + } else { + // A regular memory access. + cycle.apply( + ®ions_[address >> 18].contents[address], + regions_[address >> 18].read_write_mask + ); } - cycle.apply(®ions_[address >> 18].contents[address], regions_[address >> 18].read_write_mask); return HalfCycles(0); }