6502/CLK
1
0
Fork 0
mirror of https://github.com/TomHarte/CLK.git synced 2024-11-28 21:49:27 +00:00
Code Issues Projects Releases Wiki Activity

Gets to what is probably a CIA access?

Browse Source
This commit is contained in:
Thomas Harte 2021-07-17 21:36:20 -04:00
parent a0a9a72d8f
commit b1616be4b8
1 changed files with 24 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

28
Machines/Amiga/Amiga.cpp
View File

@ -79,11 +79,31 @@ class ConcreteMachine:
// Grab the target address to pick a memory source. // Grab the target address to pick a memory source.
const uint32_t address = cycle.host_endian_byte_address(); const uint32_t address = cycle.host_endian_byte_address();
if(!regions_[address >> 18].read_write_mask) { if(cycle.operation & (Microcycle::SelectByte | Microcycle::SelectWord)) {
// TODO: registers, etc, here. printf("%06x\n", address);
assert(false); }
if(!regions_[address >> 18].read_write_mask) {
if((cycle.operation & (Microcycle::SelectByte | Microcycle::SelectWord))) {
// Check for various potential chip accesses.
if(address >= 0xbf'd000 && address <= 0xbf'ef01) {
printf("Unimplemented CIA %06x\n", address);
assert(false);
} else if(address >= 0xdf'f000 && address <= 0xdf'f1be) {
printf("Unimplemented chipset access %06x\n", address);
assert(false);
} else {
// This'll do for open bus, for now.
cycle.set_value16(0xffff);
}
}
} else {
// A regular memory access.
cycle.apply(
&regions_[address >> 18].contents[address],
regions_[address >> 18].read_write_mask
);
} }
cycle.apply(&regions_[address >> 18].contents[address], regions_[address >> 18].read_write_mask);
return HalfCycles(0); return HalfCycles(0);
} }