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https://github.com/TomHarte/CLK.git
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Eliminated the 6502's reliance on the micro-op scheduler.
This commit is contained in:
Thomas Harte
parent
3ceef2005b
commit
b304c3a4b9
@ -559,7 +559,6 @@
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4B6C73BC1D387AE500AFCFCA /* DiskController.hpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.h; path = DiskController.hpp; sourceTree = "<group>"; };
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4B77069C1EC904570053B588 /* Z80.hpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.h; name = Z80.hpp; path = Z80/Z80.hpp; sourceTree = "<group>"; };
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4B7706A01EC9398D0053B588 /* MicroOpScheduler.hpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.h; path = MicroOpScheduler.hpp; sourceTree = "<group>"; };
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4B7913CA1DFCD80E00175A82 /* Video.cpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.cpp; name = Video.cpp; path = Electron/Video.cpp; sourceTree = "<group>"; };
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4B7913CB1DFCD80E00175A82 /* Video.hpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.h; name = Video.hpp; path = Electron/Video.hpp; sourceTree = "<group>"; };
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4B79E4411E3AF38600141F11 /* cassette.png */ = {isa = PBXFileReference; lastKnownFileType = image.png; path = cassette.png; sourceTree = "<group>"; };
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@ -1838,7 +1837,6 @@
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children = (
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4B1414561B58879D00E04248 /* 6502 */,
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4B77069E1EC9045B0053B588 /* Z80 */,
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4B7706A01EC9398D0053B588 /* MicroOpScheduler.hpp */,
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4B2C455C1EC9442600FC74DD /* RegisterSizes.hpp */,
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4BFCA1211ECBDCAF00AC40C1 /* AllRAMProcessor.cpp */,
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4BFCA1221ECBDCAF00AC40C1 /* AllRAMProcessor.hpp */,
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@ -12,7 +12,6 @@
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#include <cstdio>
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#include <cstdint>
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#include "../MicroOpScheduler.hpp"
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#include "../RegisterSizes.hpp"
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namespace CPU {
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@ -67,51 +66,6 @@ enum BusOperation {
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*/
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extern const uint8_t JamOpcode;
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/*
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This emulation functions by decomposing instructions into micro programs, consisting of the micro operations
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as per the enum below. Each micro op takes at most one cycle. By convention, those called CycleX take a cycle
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to perform whereas those called OperationX occur for free (so, in effect, their cost is loaded onto the next cycle).
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*/
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enum MicroOp {
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CycleFetchOperation, CycleFetchOperand, OperationDecodeOperation, CycleIncPCPushPCH,
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CyclePushPCH, CyclePushPCL, CyclePushA, CyclePushOperand,
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OperationSetI,
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OperationBRKPickVector, OperationNMIPickVector, OperationRSTPickVector,
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CycleReadVectorLow, CycleReadVectorHigh,
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CycleReadFromS, CycleReadFromPC,
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CyclePullOperand, CyclePullPCL, CyclePullPCH, CyclePullA,
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CycleNoWritePush,
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CycleReadAndIncrementPC, CycleIncrementPCAndReadStack, CycleIncrementPCReadPCHLoadPCL, CycleReadPCHLoadPCL,
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CycleReadAddressHLoadAddressL, CycleReadPCLFromAddress, CycleReadPCHFromAddress, CycleLoadAddressAbsolute,
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OperationLoadAddressZeroPage, CycleLoadAddessZeroX, CycleLoadAddessZeroY, CycleAddXToAddressLow,
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CycleAddYToAddressLow, CycleAddXToAddressLowRead, OperationCorrectAddressHigh, CycleAddYToAddressLowRead,
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OperationMoveToNextProgram, OperationIncrementPC,
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CycleFetchOperandFromAddress, CycleWriteOperandToAddress, OperationCopyOperandFromA, OperationCopyOperandToA,
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CycleIncrementPCFetchAddressLowFromOperand, CycleAddXToOperandFetchAddressLow, CycleIncrementOperandFetchAddressHigh, OperationDecrementOperand,
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OperationIncrementOperand, OperationORA, OperationAND, OperationEOR,
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OperationINS, OperationADC, OperationSBC, OperationLDA,
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OperationLDX, OperationLDY, OperationLAX, OperationSTA,
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OperationSTX, OperationSTY, OperationSAX, OperationSHA,
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OperationSHX, OperationSHY, OperationSHS, OperationCMP,
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OperationCPX, OperationCPY, OperationBIT, OperationASL,
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OperationASO, OperationROL, OperationRLA, OperationLSR,
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OperationLSE, OperationASR, OperationROR, OperationRRA,
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OperationCLC, OperationCLI, OperationCLV, OperationCLD,
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OperationSEC, OperationSEI, OperationSED, OperationINC,
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OperationDEC, OperationINX, OperationDEX, OperationINY,
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OperationDEY, OperationBPL, OperationBMI, OperationBVC,
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OperationBVS, OperationBCC, OperationBCS, OperationBNE,
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OperationBEQ, OperationTXA, OperationTYA, OperationTXS,
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OperationTAY, OperationTAX, OperationTSX, OperationARR,
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OperationSBX, OperationLXA, OperationANE, OperationANC,
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OperationLAS, CycleAddSignedOperandToPC, OperationSetFlagsFromOperand, OperationSetOperandFromFlagsWithBRKSet,
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OperationSetOperandFromFlags,
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OperationSetFlagsFromA,
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CycleScheduleJam
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};
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/*!
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@abstact An abstract base class for emulation of a 6502 processor via the curiously recurring template pattern/f-bounded polymorphism.
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@ -123,7 +77,7 @@ enum MicroOp {
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that will cause call outs when the program counter reaches those addresses. @c return_from_subroutine can be used to exit from a
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jammed state.
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*/
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template <class T> class Processor: public MicroOpScheduler<MicroOp> {
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template <class T> class Processor {
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public:
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class JamHandler {
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@ -133,7 +87,53 @@ template <class T> class Processor: public MicroOpScheduler<MicroOp> {
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private:
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#define JAM {CycleFetchOperand, CycleScheduleJam, OperationMoveToNextProgram}
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/*
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This emulation functions by decomposing instructions into micro programs, consisting of the micro operations
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as per the enum below. Each micro op takes at most one cycle. By convention, those called CycleX take a cycle
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to perform whereas those called OperationX occur for free (so, in effect, their cost is loaded onto the next cycle).
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*/
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enum MicroOp {
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CycleFetchOperation, CycleFetchOperand, OperationDecodeOperation, CycleIncPCPushPCH,
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CyclePushPCH, CyclePushPCL, CyclePushA, CyclePushOperand,
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OperationSetI,
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OperationBRKPickVector, OperationNMIPickVector, OperationRSTPickVector,
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CycleReadVectorLow, CycleReadVectorHigh,
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CycleReadFromS, CycleReadFromPC,
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CyclePullOperand, CyclePullPCL, CyclePullPCH, CyclePullA,
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CycleNoWritePush,
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CycleReadAndIncrementPC, CycleIncrementPCAndReadStack, CycleIncrementPCReadPCHLoadPCL, CycleReadPCHLoadPCL,
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CycleReadAddressHLoadAddressL, CycleReadPCLFromAddress, CycleReadPCHFromAddress, CycleLoadAddressAbsolute,
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OperationLoadAddressZeroPage, CycleLoadAddessZeroX, CycleLoadAddessZeroY, CycleAddXToAddressLow,
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CycleAddYToAddressLow, CycleAddXToAddressLowRead, OperationCorrectAddressHigh, CycleAddYToAddressLowRead,
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OperationMoveToNextProgram, OperationIncrementPC,
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CycleFetchOperandFromAddress, CycleWriteOperandToAddress, OperationCopyOperandFromA, OperationCopyOperandToA,
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CycleIncrementPCFetchAddressLowFromOperand, CycleAddXToOperandFetchAddressLow, CycleIncrementOperandFetchAddressHigh, OperationDecrementOperand,
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OperationIncrementOperand, OperationORA, OperationAND, OperationEOR,
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OperationINS, OperationADC, OperationSBC, OperationLDA,
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OperationLDX, OperationLDY, OperationLAX, OperationSTA,
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OperationSTX, OperationSTY, OperationSAX, OperationSHA,
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OperationSHX, OperationSHY, OperationSHS, OperationCMP,
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OperationCPX, OperationCPY, OperationBIT, OperationASL,
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OperationASO, OperationROL, OperationRLA, OperationLSR,
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OperationLSE, OperationASR, OperationROR, OperationRRA,
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OperationCLC, OperationCLI, OperationCLV, OperationCLD,
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OperationSEC, OperationSEI, OperationSED, OperationINC,
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OperationDEC, OperationINX, OperationDEX, OperationINY,
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OperationDEY, OperationBPL, OperationBMI, OperationBVC,
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OperationBVS, OperationBCC, OperationBCS, OperationBNE,
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OperationBEQ, OperationTXA, OperationTYA, OperationTXS,
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OperationTAY, OperationTAX, OperationTSX, OperationARR,
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OperationSBX, OperationLXA, OperationANE, OperationANC,
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OperationLAS, CycleAddSignedOperandToPC, OperationSetFlagsFromOperand, OperationSetOperandFromFlagsWithBRKSet,
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OperationSetOperandFromFlags,
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OperationSetFlagsFromA,
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CycleScheduleJam
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};
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const MicroOp *scheduled_program_counter_;
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#define JAM {CycleFetchOperand, CycleScheduleJam}
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/*
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Storage for the 6502 registers; F is stored as individual flags.
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@ -422,7 +422,7 @@ template <class T> class Processor: public MicroOpScheduler<MicroOp> {
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#undef Immediate
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#undef Implied
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schedule_program(operations[operation]);
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scheduled_program_counter_ = operations[operation];
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}
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bool is_jammed_;
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@ -522,7 +522,8 @@ template <class T> class Processor: public MicroOpScheduler<MicroOp> {
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interrupt_requests_(InterruptRequestFlags::PowerOn),
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irq_line_(0),
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nmi_line_is_enabled_(false),
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set_overflow_line_is_enabled_(false) {
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set_overflow_line_is_enabled_(false),
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scheduled_program_counter_(nullptr) {
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// only the interrupt flag is defined upon reset but get_flags isn't going to
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// mask the other flags so we need to do that, at least
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carry_flag_ &= Flag::Carry;
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@ -550,8 +551,7 @@ template <class T> class Processor: public MicroOpScheduler<MicroOp> {
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static const MicroOp fetch_decode_execute[] = {
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CycleFetchOperation,
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CycleFetchOperand,
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OperationDecodeOperation,
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OperationMoveToNextProgram
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OperationDecodeOperation
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};
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// These plus program below act to give the compiler permission to update these values
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@ -564,19 +564,18 @@ template <class T> class Processor: public MicroOpScheduler<MicroOp> {
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#define checkSchedule(op) \
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if(!scheduled_program_counter_) {\
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schedule_programs_read_pointer_ = schedule_programs_write_pointer_ = 0; \
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if(interrupt_requests_) {\
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if(interrupt_requests_ & (InterruptRequestFlags::Reset | InterruptRequestFlags::PowerOn)) {\
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interrupt_requests_ &= ~InterruptRequestFlags::PowerOn;\
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schedule_program(get_reset_program());\
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scheduled_program_counter_ = get_reset_program();\
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} else if(interrupt_requests_ & InterruptRequestFlags::NMI) {\
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interrupt_requests_ &= ~InterruptRequestFlags::NMI;\
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schedule_program(get_nmi_program());\
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scheduled_program_counter_ = get_nmi_program();\
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} else if(interrupt_requests_ & InterruptRequestFlags::IRQ) {\
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schedule_program(get_irq_program());\
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scheduled_program_counter_ = get_irq_program();\
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} \
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} else {\
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schedule_program(fetch_decode_execute);\
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scheduled_program_counter_ = fetch_decode_execute;\
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}\
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op;\
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}
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@ -644,7 +643,7 @@ template <class T> class Processor: public MicroOpScheduler<MicroOp> {
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continue;
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case OperationMoveToNextProgram:
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move_to_next_program();
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scheduled_program_counter_ = nullptr;
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checkSchedule();
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continue;
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@ -704,7 +703,7 @@ template <class T> class Processor: public MicroOpScheduler<MicroOp> {
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case CycleScheduleJam: {
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is_jammed_ = true;
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static const MicroOp jam[] = JAM;
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schedule_program(jam);
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scheduled_program_counter_ = jam;
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if(jam_handler_) {
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jam_handler_->processor_did_jam(this, pc_.full - 1);
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@ -1003,7 +1002,7 @@ template <class T> class Processor: public MicroOpScheduler<MicroOp> {
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#pragma mark - Branching
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#define BRA(condition) pc_.full++; if(condition) schedule_program(doBranch)
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#define BRA(condition) pc_.full++; if(condition) scheduled_program_counter_ = doBranch
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case OperationBPL: BRA(!(negative_result_&0x80)); continue;
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case OperationBMI: BRA(negative_result_&0x80); continue;
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@ -1145,7 +1144,6 @@ template <class T> class Processor: public MicroOpScheduler<MicroOp> {
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pc_.full++;
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if(is_jammed_) {
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scheduled_programs_[0] = scheduled_programs_[1] = scheduled_programs_[2] = scheduled_programs_[3] = nullptr;
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scheduled_program_counter_ = nullptr;
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}
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}
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@ -19,6 +19,8 @@ AllRAMProcessor::AllRAMProcessor() : ::CPU::AllRAMProcessor(65536) {
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int AllRAMProcessor::perform_bus_operation(MOS6502::BusOperation operation, uint16_t address, uint8_t *value) {
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timestamp_++;
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// if(operation == MOS6502::BusOperation::ReadOpcode) printf("%04x\n", address);
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if(isReadOperation(operation)) {
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*value = memory_[address];
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} else {
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@ -1,56 +0,0 @@
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//
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// MicroOpScheduler.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 14/05/2017.
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// Copyright © 2017 Thomas Harte. All rights reserved.
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//
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#ifndef MicroOpScheduler_hpp
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#define MicroOpScheduler_hpp
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namespace CPU {
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template <class T> class MicroOpScheduler {
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public:
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MicroOpScheduler() :
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scheduled_programs_{nullptr, nullptr, nullptr, nullptr},
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schedule_programs_write_pointer_(0),
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schedule_programs_read_pointer_(0),
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scheduled_program_counter_(nullptr) {}
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protected:
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/*
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Up to four programs can be scheduled; each will be carried out in turn. This
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storage maintains pointers to the scheduled list of programs.
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Programs should be terminated by an OperationMoveToNextProgram, causing this
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queue to take that step.
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*/
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const T *scheduled_programs_[4];
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const T *scheduled_program_counter_;
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unsigned int schedule_programs_write_pointer_, schedule_programs_read_pointer_;
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/*!
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Schedules a new program, adding it to the end of the queue. Programs should be
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terminated with a OperationMoveToNextProgram. No attempt to copy the program
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is made; a non-owning reference is kept.
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@param program The program to schedule.
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*/
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inline void schedule_program(const T *program) {
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scheduled_programs_[schedule_programs_write_pointer_] = program;
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if(schedule_programs_write_pointer_ == schedule_programs_read_pointer_) scheduled_program_counter_ = program;
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schedule_programs_write_pointer_ = (schedule_programs_write_pointer_+1)&3;
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}
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inline void move_to_next_program() {
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scheduled_programs_[schedule_programs_read_pointer_] = nullptr;
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schedule_programs_read_pointer_ = (schedule_programs_read_pointer_+1)&3;
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scheduled_program_counter_ = scheduled_programs_[schedule_programs_read_pointer_];
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}
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};
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}
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#endif /* MicroOpScheduler_hpp */
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