diff --git a/Processors/6502/Implementation/6502Implementation.hpp b/Processors/6502/Implementation/6502Implementation.hpp
index 98879f6c2..47e0bcfc9 100644
--- a/Processors/6502/Implementation/6502Implementation.hpp
+++ b/Processors/6502/Implementation/6502Implementation.hpp
@@ -537,8 +537,6 @@ if(number_of_cycles <= Cycles(0)) break;
 	pc_.full++; \
 	if(condition) {	\
 		scheduled_program_counter_ = do_branch;	\
-	} else if(is_65c02(personality)) {	\
-		scheduled_program_counter_ = fetch_decode_execute;	\
 	}
 
 					case OperationBPL: BRA(!(negative_result_&0x80));				continue;
@@ -551,6 +549,8 @@ if(number_of_cycles <= Cycles(0)) break;
 					case OperationBEQ: BRA(!zero_result_);							continue;
 					case OperationBRA: BRA(true);									continue;
 
+#undef BRA
+
 					case CycleAddSignedOperandToPC:
 						nextAddress.full = static_cast<uint16_t>(pc_.full + (int8_t)operand_);
 						pc_.bytes.low = nextAddress.bytes.low;
@@ -559,6 +559,11 @@ if(number_of_cycles <= Cycles(0)) break;
 							pc_.full = nextAddress.full;
 							throwaway_read(halfUpdatedPc);
 							break;
+						} else if(is_65c02(personality)) {
+							// 65C02 modification to all branches: a branch that is taken but requires only a single cycle
+							// to target its destination skips any pending interrupts.
+							// Cf. http://forum.6502.org/viewtopic.php?f=4&t=1634
+							scheduled_program_counter_ = fetch_decode_execute;
 						}
 					continue;
 
@@ -595,8 +600,6 @@ if(number_of_cycles <= Cycles(0)) break;
 						}
 					} break;
 
-#undef BRA
-
 // MARK: - Transfers
 
 					case OperationTXA: zero_result_ = negative_result_ = a_ = x_;	continue;
diff --git a/Processors/6502/Implementation/6502Storage.hpp b/Processors/6502/Implementation/6502Storage.hpp
index a8266a55f..e877c4c98 100644
--- a/Processors/6502/Implementation/6502Storage.hpp
+++ b/Processors/6502/Implementation/6502Storage.hpp
@@ -162,9 +162,6 @@ class ProcessorStorage {
 			OperationBNE,	// schedules the branch program if the zero flag is clear
 			OperationBEQ,	// schedules the branch program if the zero flag is set; 65C02: otherwise jumps straight into a fetch-decode-execute without considering whether to take an interrupt
 			OperationBRA,	// schedules the branch program
-			// 65C02 modification to all branches: if the branch isn't taken, the next fetch-decode-execute
-			// sequence is scheduled immediately, without any possibility of responding to an interrupt.
-			// Cf. http://forum.6502.org/viewtopic.php?f=4&t=1634
 
 			OperationBBRBBS,	// inspecting the operation_, if the appropriate bit of operand_ is set or clear schedules a program to read and act upon the second operand; otherwise schedule a program to read and discard it
 
@@ -184,7 +181,7 @@ class ProcessorStorage {
 			OperationLAS,	// loads a, x and s with s & operand, setting the negative and zero flags
 
 			CycleFetchFromHalfUpdatedPC,		// performs a throwaway read from (PC + (signed)operand).l combined with PC.h
-			CycleAddSignedOperandToPC,			// sets next_address to PC + (signed)operand. If the high byte of next_address differs from the PC, schedules a throwaway read from the half-updated PC
+			CycleAddSignedOperandToPC,			// sets next_address to PC + (signed)operand. If the high byte of next_address differs from the PC, schedules a throwaway read from the half-updated PC. 65C02 specific: if the top two bytes are the same, proceeds directly to fetch-decode-execute, ignoring any pending interrupts.
 			OperationAddSignedOperandToPC16,	// adds (signed)operand into the PC
 
 			OperationSetFlagsFromOperand,			// sets all flags based on operand_