mirror of
https://github.com/TomHarte/CLK.git
synced 2024-11-26 08:49:37 +00:00
Consume operand_flags into Instruction.hpp.
This commit is contained in:
Thomas Harte
parent
c61809f0c4
commit
b3cf13775b
@ -13,7 +13,6 @@
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#include "Instruction.hpp"
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#include "Model.hpp"
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#include "Perform.hpp"
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#include "Sequence.hpp"
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#include "Status.hpp"
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namespace InstructionSet {
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@ -108,7 +108,7 @@ typename Executor<model, BusHandler>::EffectiveAddress Executor<model, BusHandle
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ea.requires_fetch = false;
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break;
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case AddressingMode::Quick:
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ea.value.l = quick(instruction.operation, opcode);
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ea.value.l = quick(opcode, instruction.operation);
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ea.requires_fetch = false;
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break;
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case AddressingMode::ImmediateData:
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@ -9,9 +9,11 @@
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#ifndef InstructionSets_68k_Instruction_hpp
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#define InstructionSets_68k_Instruction_hpp
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#include <cstdint>
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#include "Model.hpp"
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#include <cassert>
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#include <cstdint>
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namespace InstructionSet {
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namespace M68k {
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@ -224,9 +226,9 @@ constexpr DataSize size(Operation operation) {
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}
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}
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template <Operation op>
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constexpr uint32_t quick(uint16_t instruction) {
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switch(op) {
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template <Operation t_op = Operation::Undefined>
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constexpr uint32_t quick(uint16_t instruction, Operation r_op = Operation::Undefined) {
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switch((t_op != Operation::Undefined) ? t_op : r_op) {
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case Operation::Bccb:
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case Operation::BSRb:
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case Operation::MOVEl: return uint32_t(int8_t(instruction));
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@ -239,16 +241,85 @@ constexpr uint32_t quick(uint16_t instruction) {
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}
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}
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constexpr uint32_t quick(Operation op, uint16_t instruction) {
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switch(op) {
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case Operation::MOVEl: return quick<Operation::MOVEl>(instruction);
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case Operation::Bccb: return quick<Operation::Bccb>(instruction);
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case Operation::BSRb: return quick<Operation::BSRb>(instruction);
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case Operation::TRAP: return quick<Operation::TRAP>(instruction);
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static constexpr uint8_t FetchOp1 = (1 << 0);
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static constexpr uint8_t FetchOp2 = (1 << 1);
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static constexpr uint8_t StoreOp1 = (1 << 2);
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static constexpr uint8_t StoreOp2 = (1 << 3);
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/*!
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Provides a bitfield with a value in the range 0–15 indicating which of the provided operation's
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operands are accessed via standard fetch and store cycles.
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Unusual bus sequences, such as TAS or MOVEM, are not described here.
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*/
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template <Model model, Operation t_operation = Operation::Undefined> uint8_t operand_flags(Operation r_operation = Operation::Undefined) {
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switch((t_operation != Operation::Undefined) ? t_operation : r_operation) {
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default:
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// ADDw is arbitrary; anything other than those listed above will do.
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return quick<Operation::ADDw>(instruction);
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assert(false);
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//
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// No operands are fetched or stored.
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//
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case Operation::LEA:
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case Operation::PEA:
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return 0;
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//
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// Single-operand read.
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//
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case Operation::MOVEtoSR: case Operation::MOVEtoCCR: case Operation::MOVEtoUSP:
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case Operation::ORItoSR: case Operation::ORItoCCR:
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case Operation::ANDItoSR: case Operation::ANDItoCCR:
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case Operation::EORItoSR: case Operation::EORItoCCR:
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return FetchOp1;
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//
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// Single-operand write.
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//
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case Operation::MOVEfromSR: case Operation::MOVEfromUSP:
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return StoreOp1;
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//
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// Single-operand read-modify-write.
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//
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case Operation::NBCD:
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case Operation::EXTbtow: case Operation::EXTwtol:
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return FetchOp1 | StoreOp1;
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//
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// Two-operand; read both.
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//
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case Operation::CMPb: case Operation::CMPw: case Operation::CMPl:
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case Operation::CMPAw: case Operation::CMPAl:
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return FetchOp1 | FetchOp2;
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//
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// Two-operand; read source, write dest.
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//
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case Operation::MOVEb: case Operation::MOVEw: case Operation::MOVEl:
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case Operation::MOVEAw: case Operation::MOVEAl:
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return FetchOp1 | StoreOp2;
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//
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// Two-operand; read both, write dest.
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//
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case Operation::ABCD: case Operation::SBCD:
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case Operation::ADDb: case Operation::ADDw: case Operation::ADDl:
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case Operation::ADDAw: case Operation::ADDAl:
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case Operation::ADDXb: case Operation::ADDXw: case Operation::ADDXl:
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case Operation::SUBb: case Operation::SUBw: case Operation::SUBl:
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case Operation::SUBAw: case Operation::SUBAl:
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case Operation::SUBXb: case Operation::SUBXw: case Operation::SUBXl:
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case Operation::ORb: case Operation::ORw: case Operation::ORl:
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case Operation::ANDb: case Operation::ANDw: case Operation::ANDl:
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case Operation::EORb: case Operation::EORw: case Operation::EORl:
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return FetchOp1 | FetchOp2 | StoreOp2;
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//
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// Two-operand; read both, write both.
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//
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case Operation::EXG:
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return FetchOp1 | FetchOp2 | StoreOp1 | StoreOp2;
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}
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}
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@ -1,114 +0,0 @@
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//
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// Sequence.cpp
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// Clock Signal
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//
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// Created by Thomas Harte on 29/04/2022.
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// Copyright © 2022 Thomas Harte. All rights reserved.
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//
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#include "Sequence.hpp"
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#include <cassert>
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using namespace InstructionSet::M68k;
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/*
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template <Step... T> struct Steps {
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static constexpr uint32_t value = 0;
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};
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template <Step F, Step... T> struct Steps<F, T...> {
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static constexpr uint32_t value = uint16_t(F) | uint16_t(Steps<T...>::value << 4);
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};
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template<Model model> uint32_t Sequence<model>::steps_for(Operation operation) {
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switch(operation) {
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// This handles a NOP, and not much else.
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default: assert(false);
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//
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// No operands that require fetching.
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//
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case Operation::LEA:
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return Steps<
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Step::Perform
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>::value;
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//
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// No logic, custom bus activity required.
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//
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case Operation::PEA:
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return Steps<
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Step::SpecificBusActivity
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>::value;
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//
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// Single operand, read.
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//
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case Operation::MOVEtoSR: case Operation::MOVEtoCCR: case Operation::MOVEtoUSP:
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case Operation::ORItoSR: case Operation::ORItoCCR:
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case Operation::ANDItoSR: case Operation::ANDItoCCR:
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case Operation::EORItoSR: case Operation::EORItoCCR:
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return Steps<
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Step::FetchOp1,
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Step::Perform
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>::value;
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//
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// Single operand, write.
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//
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case Operation::MOVEfromSR: case Operation::MOVEfromUSP:
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return Steps<
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Step::Perform,
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Step::StoreOp1
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>::value;
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//
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// Single operand, read-modify-write.
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//
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case Operation::NBCD:
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case Operation::EXTbtow: case Operation::EXTwtol:
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return Steps<
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Step::FetchOp1,
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Step::Perform,
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Step::StoreOp1
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>::value;
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//
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// Two operand, read-write.
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//
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case Operation::MOVEb: case Operation::MOVEw: case Operation::MOVEl:
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case Operation::MOVEAw: case Operation::MOVEAl:
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return Steps<
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Step::FetchOp1,
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Step::Perform,
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Step::StoreOp2
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>::value;
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//
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// Two operand, read-modify-write.
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//
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case Operation::ABCD: case Operation::SBCD:
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case Operation::ADDb: case Operation::ADDw: case Operation::ADDl:
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case Operation::ADDAw: case Operation::ADDAl:
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case Operation::ADDXb: case Operation::ADDXw: case Operation::ADDXl:
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case Operation::SUBb: case Operation::SUBw: case Operation::SUBl:
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case Operation::SUBAw: case Operation::SUBAl:
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case Operation::SUBXb: case Operation::SUBXw: case Operation::SUBXl:
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return Steps<
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Step::FetchOp1,
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Step::FetchOp2,
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Step::Perform,
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Step::StoreOp2
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>::value;
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}
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}
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template<Model model> Sequence<model>::Sequence(Operation operation) : steps_(steps_for(operation)) {}
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template class InstructionSet::M68k::Sequence<Model::M68000>;
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template class InstructionSet::M68k::Sequence<Model::M68010>;
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template class InstructionSet::M68k::Sequence<Model::M68020>;
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template class InstructionSet::M68k::Sequence<Model::M68030>;
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template class InstructionSet::M68k::Sequence<Model::M68040>;
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*/
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@ -1,106 +0,0 @@
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//
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// Sequencer.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 29/04/2022.
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// Copyright © 2022 Thomas Harte. All rights reserved.
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//
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#ifndef InstructionSets_68k_Sequencer_hpp
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#define InstructionSets_68k_Sequencer_hpp
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#include "Instruction.hpp"
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#include "Model.hpp"
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#include <cassert>
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namespace InstructionSet {
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namespace M68k {
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static constexpr uint8_t FetchOp1 = (1 << 0);
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static constexpr uint8_t FetchOp2 = (1 << 1);
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static constexpr uint8_t StoreOp1 = (1 << 2);
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static constexpr uint8_t StoreOp2 = (1 << 3);
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/*!
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Provides a bitfield with a value in the range 0–15 indicating which of the provided operation's
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operands are accessed via standard fetch and store cycles.
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Unusual bus sequences, such as TAS or MOVEM, are not described here.
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*/
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template <Model model, Operation t_operation = Operation::Undefined> uint8_t operand_flags(Operation r_operation = Operation::Undefined) {
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switch((t_operation != Operation::Undefined) ? t_operation : r_operation) {
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default:
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assert(false);
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//
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// No operands are fetched or stored.
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//
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case Operation::LEA:
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case Operation::PEA:
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return 0;
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//
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// Single-operand read.
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//
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case Operation::MOVEtoSR: case Operation::MOVEtoCCR: case Operation::MOVEtoUSP:
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case Operation::ORItoSR: case Operation::ORItoCCR:
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case Operation::ANDItoSR: case Operation::ANDItoCCR:
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case Operation::EORItoSR: case Operation::EORItoCCR:
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return FetchOp1;
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//
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// Single-operand write.
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//
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case Operation::MOVEfromSR: case Operation::MOVEfromUSP:
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return StoreOp1;
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//
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// Single-operand read-modify-write.
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//
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case Operation::NBCD:
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case Operation::EXTbtow: case Operation::EXTwtol:
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return FetchOp1 | StoreOp1;
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//
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// Two-operand; read both.
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//
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case Operation::CMPb: case Operation::CMPw: case Operation::CMPl:
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case Operation::CMPAw: case Operation::CMPAl:
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return FetchOp1 | FetchOp2;
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//
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// Two-operand; read source, write dest.
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//
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case Operation::MOVEb: case Operation::MOVEw: case Operation::MOVEl:
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case Operation::MOVEAw: case Operation::MOVEAl:
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return FetchOp1 | StoreOp2;
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//
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// Two-operand; read both, write dest.
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//
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case Operation::ABCD: case Operation::SBCD:
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case Operation::ADDb: case Operation::ADDw: case Operation::ADDl:
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case Operation::ADDAw: case Operation::ADDAl:
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case Operation::ADDXb: case Operation::ADDXw: case Operation::ADDXl:
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case Operation::SUBb: case Operation::SUBw: case Operation::SUBl:
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case Operation::SUBAw: case Operation::SUBAl:
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case Operation::SUBXb: case Operation::SUBXw: case Operation::SUBXl:
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case Operation::ORb: case Operation::ORw: case Operation::ORl:
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case Operation::ANDb: case Operation::ANDw: case Operation::ANDl:
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case Operation::EORb: case Operation::EORw: case Operation::EORl:
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return FetchOp1 | FetchOp2 | StoreOp2;
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//
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// Two-operand; read both, write both.
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//
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case Operation::EXG:
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return FetchOp1 | FetchOp2 | StoreOp1 | StoreOp2;
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}
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}
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}
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}
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#endif /* InstructionSets_68k_Sequencer_h */
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@ -427,8 +427,6 @@
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@ -1427,8 +1425,6 @@
|
||||
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|
||||
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@ -3167,13 +3163,11 @@
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4B79629E2819681F008130F9 /* Decoder.hpp */,
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||||
4BB5B99C281C805300522DA9 /* Executor.hpp */,
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4B79629C2819681F008130F9 /* Instruction.hpp */,
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4B79629D2819681F008130F9 /* Model.hpp */,
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4B7962A3281C1B76008130F9 /* Sequence.hpp */,
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4BB5B999281B244400522DA9 /* Implementation */,
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@ -7,9 +7,9 @@
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||||
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||||
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|
||||
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shouldUseLaunchSchemeArgsEnv = "YES">
|
||||
<Testables>
|
||||
<TestableReference
|
||||
|
||||
@ -15,6 +15,8 @@
|
||||
#include <memory>
|
||||
#include <functional>
|
||||
|
||||
#define USE_EXISTING_IMPLEMENTATION
|
||||
|
||||
@interface M68000ComparativeTests : XCTestCase
|
||||
@end
|
||||
|
||||
@ -73,7 +75,11 @@
|
||||
// Perform each dictionary in the array as a test.
|
||||
for(NSDictionary *test in jsonContents) {
|
||||
if(![test isKindOfClass:[NSDictionary class]]) continue;
|
||||
#ifdef USE_EXISTING_IMPLEMENTATION
|
||||
[self testOperationClassic:test];
|
||||
#else
|
||||
[self testOperationExecutor:test];
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -54,7 +54,7 @@ template <int index> NSString *operand(Preinstruction instruction, uint16_t opco
|
||||
return @"#";
|
||||
|
||||
case AddressingMode::Quick:
|
||||
return [NSString stringWithFormat:@"%d", quick(instruction.operation, opcode)];
|
||||
return [NSString stringWithFormat:@"%d", quick(opcode, instruction.operation)];
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user