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Push disk data onwards.
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@ -37,8 +37,8 @@ Chipset::Chipset(MemoryMap &map, int input_clock_rate) :
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blitter_(*this, reinterpret_cast<uint16_t *>(map.chip_ram.data()), map.chip_ram.size() >> 1),
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blitter_(*this, reinterpret_cast<uint16_t *>(map.chip_ram.data()), map.chip_ram.size() >> 1),
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bitplanes_(*this, reinterpret_cast<uint16_t *>(map.chip_ram.data()), map.chip_ram.size() >> 1),
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bitplanes_(*this, reinterpret_cast<uint16_t *>(map.chip_ram.data()), map.chip_ram.size() >> 1),
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copper_(*this, reinterpret_cast<uint16_t *>(map.chip_ram.data()), map.chip_ram.size() >> 1),
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copper_(*this, reinterpret_cast<uint16_t *>(map.chip_ram.data()), map.chip_ram.size() >> 1),
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disk_controller_(Cycles(input_clock_rate)),
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disk_(*this, reinterpret_cast<uint16_t *>(map.chip_ram.data()), map.chip_ram.size() >> 1),
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disk_(*this, reinterpret_cast<uint16_t *>(map.chip_ram.data()), map.chip_ram.size() >> 1),
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disk_controller_(Cycles(input_clock_rate), disk_),
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crt_(908, 4, Outputs::Display::Type::PAL50, Outputs::Display::InputDataType::Red4Green4Blue4),
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crt_(908, 4, Outputs::Display::Type::PAL50, Outputs::Display::InputDataType::Red4Green4Blue4),
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cia_a_handler_(map, disk_controller_),
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cia_a_handler_(map, disk_controller_),
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cia_b_handler_(disk_controller_),
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cia_b_handler_(disk_controller_),
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@ -904,6 +904,11 @@ void Chipset::Sprite::set_image_data(int slot, uint16_t value) {
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// MARK: - Disk.
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// MARK: - Disk.
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void Chipset::DiskDMA::enqueue(uint16_t value, bool matches_sync) {
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(void)value;
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(void)matches_sync;
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}
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bool Chipset::DiskDMA::advance() {
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bool Chipset::DiskDMA::advance() {
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if(!dma_enable_) return false;
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if(!dma_enable_) return false;
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@ -1031,8 +1036,9 @@ void Chipset::set_component_prefers_clocking(ClockingHint::Source *, ClockingHin
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// MARK: - Disk Controller.
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// MARK: - Disk Controller.
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Chipset::DiskController::DiskController(Cycles clock_rate) :
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Chipset::DiskController::DiskController(Cycles clock_rate, DiskDMA &disk_dma) :
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Storage::Disk::Controller(clock_rate) {
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Storage::Disk::Controller(clock_rate),
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disk_dma_(disk_dma) {
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// Add four drives.
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// Add four drives.
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for(int c = 0; c < 4; c++) {
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for(int c = 0; c < 4; c++) {
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@ -1044,9 +1050,12 @@ void Chipset::DiskController::process_input_bit(int value) {
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data_ = uint16_t((data_ << 1) | value);
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data_ = uint16_t((data_ << 1) | value);
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++bit_count_;
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++bit_count_;
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// if(!(bit_count_&15)) {
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if(sync_with_word_ && data_ == sync_word_) {
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// LOG("Word: " << PADHEX(4) << data_);
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disk_dma_.enqueue(data_, true);
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// }
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bit_count_ = 0;
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} else if(!(bit_count_&15)) {
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disk_dma_.enqueue(data_, false);
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}
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}
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}
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void Chipset::DiskController::set_sync_word(uint16_t value) {
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void Chipset::DiskController::set_sync_word(uint16_t value) {
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@ -224,9 +224,33 @@ class Chipset: private ClockingHint::Observer {
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// MARK: - Disk drives.
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// MARK: - Disk drives.
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class DiskDMA: public DMADevice<1> {
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public:
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using DMADevice::DMADevice;
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void set_length(uint16_t value) {
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dma_enable_ = value & 0x8000;
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write_ = value & 0x4000;
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length_ = value & 0x3fff;
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if(dma_enable_) {
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printf("Not yet implemented: disk DMA [%s of %d to %06x]\n", write_ ? "write" : "read", length_, pointer_[0]);
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}
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}
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bool advance();
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void enqueue(uint16_t value, bool matches_sync);
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private:
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uint16_t length_;
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bool dma_enable_ = false;
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bool write_ = false;
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} disk_;
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class DiskController: public Storage::Disk::Controller {
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class DiskController: public Storage::Disk::Controller {
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public:
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public:
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DiskController(Cycles clock_rate);
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DiskController(Cycles clock_rate, DiskDMA &disk_dma);
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void set_mtr_sel_side_dir_step(uint8_t);
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void set_mtr_sel_side_dir_step(uint8_t);
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uint8_t get_rdy_trk0_wpro_chng();
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uint8_t get_rdy_trk0_wpro_chng();
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@ -255,34 +279,14 @@ class Chipset: private ClockingHint::Observer {
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uint16_t sync_word_ = 0;
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uint16_t sync_word_ = 0;
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bool sync_with_word_ = false;
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bool sync_with_word_ = false;
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DiskDMA &disk_dma_;
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} disk_controller_;
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} disk_controller_;
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void set_component_prefers_clocking(ClockingHint::Source *, ClockingHint::Preference) final;
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void set_component_prefers_clocking(ClockingHint::Source *, ClockingHint::Preference) final;
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bool disk_controller_is_sleeping_ = false;
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bool disk_controller_is_sleeping_ = false;
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uint16_t paula_disk_control_ = 0;
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uint16_t paula_disk_control_ = 0;
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class DiskDMA: public DMADevice<1> {
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public:
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using DMADevice::DMADevice;
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void set_length(uint16_t value) {
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dma_enable_ = value & 0x8000;
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write_ = value & 0x4000;
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length_ = value & 0x3fff;
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if(dma_enable_) {
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printf("Not yet implemented: disk DMA [%s of %d to %06x]\n", write_ ? "write" : "read", length_, pointer_[0]);
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}
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}
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bool advance();
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private:
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uint16_t length_;
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bool dma_enable_ = false;
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bool write_ = false;
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} disk_;
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// MARK: - Pixel output.
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// MARK: - Pixel output.
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Outputs::CRT::CRT crt_;
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Outputs::CRT::CRT crt_;
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