diff --git a/OSBindings/Mac/Clock SignalTests/68000ComparativeTests.mm b/OSBindings/Mac/Clock SignalTests/68000ComparativeTests.mm
index 0a5d610a9..4b8284679 100644
--- a/OSBindings/Mac/Clock SignalTests/68000ComparativeTests.mm	
+++ b/OSBindings/Mac/Clock SignalTests/68000ComparativeTests.mm	
@@ -156,7 +156,7 @@ struct TestProcessor: public CPU::MC68000Mk2::BusHandler {
 
 	// To limit tests run to a subset of files and/or of tests, uncomment and fill in below.
 	_fileSet = [NSSet setWithArray:@[
-		@"bcc.json",
+//		@"btst_bchg_bclr_bset.json",
 
 		// Below this line are passing tests.
 		@"abcd_sbcd.json",
@@ -164,10 +164,11 @@ struct TestProcessor: public CPU::MC68000Mk2::BusHandler {
 		@"addi_subi_cmpi.json",
 		@"addq_subq.json",
 		@"addx_subx.json",
+		@"bcc.json",
 		@"dbcc_scc.json",
 		@"eor_and_or.json",
 		@"nbcd.json",
-		@"ext.json"]];		// 9/32 = ~28% done, as far as the tests go.
+		@"ext.json"]];		// 10/32 = ~31 % done, as far as the tests go.
 //	_testSet = [NSSet setWithArray:@[@"ADDQ 05df"]];
 }
 
diff --git a/Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp b/Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp
index 1b325fb15..157b65858 100644
--- a/Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp
+++ b/Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp
@@ -96,6 +96,8 @@ enum ExecutionState: int {
 	Bcc_branch_taken,
 	Bcc_b_branch_not_taken,
 	Bcc_w_branch_not_taken,
+
+	BSR,
 };
 
 // MARK: - The state machine.
@@ -247,18 +249,18 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
 			did_update_status();
 
 			SetupDataAccess(Microcycle::Read, Microcycle::SelectWord);
-			SetDataAddress(temporary_address_);
+			SetDataAddress(temporary_address_.l);
 
-			temporary_address_ = 0;
+			temporary_address_.l = 0;
 			Access(registers_[15].high);	// nF
 
-			temporary_address_ += 2;
+			temporary_address_.l += 2;
 			Access(registers_[15].low);		// nf
 
-			temporary_address_ += 2;
+			temporary_address_.l += 2;
 			Access(program_counter_.high);	// nV
 
-			temporary_address_ += 2;
+			temporary_address_.l += 2;
 			Access(program_counter_.low);	// nv
 
 			Prefetch();			// np
@@ -293,12 +295,12 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
 
 			// Grab new program counter.
 			SetupDataAccess(Microcycle::Read, Microcycle::SelectWord);
-			SetDataAddress(temporary_address_);
+			SetDataAddress(temporary_address_.l);
 
-			temporary_address_ = exception_vector_ << 2;
+			temporary_address_.l = exception_vector_ << 2;
 			Access(program_counter_.high);	// nV
 
-			temporary_address_ += 2;
+			temporary_address_.l += 2;
 			Access(program_counter_.low);	// nv
 
 			// Populate the prefetch queue.
@@ -531,6 +533,9 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
 				StdCASE(Bccb,	perform_state_ = Bcc);
 				StdCASE(Bccw,	perform_state_ = Bcc);
 
+				StdCASE(BSRb,	perform_state_ = BSR);
+				StdCASE(BSRw,	perform_state_ = BSR);
+
 				default:
 					assert(false);
 			}
@@ -1177,6 +1182,37 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
 			Prefetch();		// np
 		MoveToState(Decode);
 
+		//
+		// BSR
+		//
+		BeginState(BSR):
+			IdleBus(1);		// n
+
+			SetupDataAccess(0, Microcycle::SelectWord);
+			SetDataAddress(registers_[15].l);
+
+			// Push the next PC to the stack; determine here what
+			// the next one should be.
+			if(instruction_.operand_size() == InstructionSet::M68k::DataSize::Word) {
+				temporary_address_.l = instruction_address_.l + 4;
+			} else {
+				temporary_address_.l = instruction_address_.l + 2;
+			}
+
+			registers_[15].l -= 4;
+			Access(temporary_address_.high);	// nS
+			registers_[15].l += 2;
+			Access(temporary_address_.low);	// ns
+			registers_[15].l -= 2;
+
+			// Get the new PC.
+			InstructionSet::M68k::perform<InstructionSet::M68k::Model::M68000>(
+				instruction_, operand_[0], operand_[1], status_, *static_cast<ProcessorBase *>(this));
+
+			Prefetch();		// np
+			Prefetch();		// np
+		MoveToState(Decode);
+
 		//
 		// Various states TODO.
 		//
@@ -1255,6 +1291,10 @@ template <typename IntT> void ProcessorBase::complete_bcc(bool take_branch, IntT
 			Bcc_b_branch_not_taken : Bcc_w_branch_not_taken;
 }
 
+void ProcessorBase::bsr(uint32_t offset) {
+	program_counter_.l = instruction_address_.l + offset + 2;
+}
+
 // MARK: - External state.
 
 template <class BusHandler, bool dtack_is_implicit, bool permit_overrun, bool signal_will_perform>
diff --git a/Processors/68000Mk2/Implementation/68000Mk2Storage.hpp b/Processors/68000Mk2/Implementation/68000Mk2Storage.hpp
index 6dea93a02..57ee1080a 100644
--- a/Processors/68000Mk2/Implementation/68000Mk2Storage.hpp
+++ b/Processors/68000Mk2/Implementation/68000Mk2Storage.hpp
@@ -79,7 +79,7 @@ struct ProcessorBase: public InstructionSet::M68k::NullFlowController {
 	/// be used to populate microcycles, which may persist beyond an entry
 	/// and exit of run_for (especially between an address announcement, and
 	/// a data select).
-	uint32_t temporary_address_ = 0;
+	SlicedInt32 temporary_address_;
 
 	/// A record of the exception to trigger.
 	int exception_vector_ = 0;
@@ -110,7 +110,7 @@ struct ProcessorBase: public InstructionSet::M68k::NullFlowController {
 	inline void did_update_status();
 	template <typename IntT> void complete_bcc(bool, IntT);
 	inline void complete_dbcc(bool, bool, int16_t);
-	inline void bsr(uint32_t) {}
+	inline void bsr(uint32_t);
 	inline void jsr(uint32_t) {}
 	inline void jmp(uint32_t) {}
 	inline void rtr() {}