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https://github.com/TomHarte/CLK.git
synced 2026-01-23 16:16:16 +00:00
Continue conversion of logging.
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@@ -23,7 +23,6 @@
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#include "../../Outputs/Speaker/Implementation/LowpassSpeaker.hpp"
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#include "../../Outputs/Speaker/Implementation/CompoundSource.hpp"
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#define LOG_PREFIX "[SMS] "
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#include "../../Outputs/Log.hpp"
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#include "../../Analyser/Static/Sega/Target.hpp"
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@@ -34,6 +33,7 @@
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namespace {
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constexpr int audio_divider = 1;
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Log::Logger<Log::Source::MasterSystem> logger;
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}
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namespace Sega {
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@@ -255,17 +255,17 @@ template <Analyser::Static::Sega::Target::Model model> class ConcreteMachine:
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}
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if(write_pointers_[address >> 10]) write_pointers_[address >> 10][address & 1023] = *cycle.value;
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// else LOG("Ignored write to ROM");
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// else logger.info().append("Ignored write to ROM");
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break;
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case CPU::Z80::PartialMachineCycle::Input:
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switch(address & 0xc1) {
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case 0x00:
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LOG("TODO: [input] memory control");
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logger.error().append("TODO: [input] memory control");
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*cycle.value = 0xff;
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break;
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case 0x01:
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LOG("TODO: [input] I/O port control");
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logger.error().append("TODO: [input] I/O port control");
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*cycle.value = 0xff;
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break;
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case 0x40:
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@@ -305,7 +305,7 @@ template <Analyser::Static::Sega::Target::Model model> class ConcreteMachine:
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} break;
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default:
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ERROR("[input] Clearly some sort of typo");
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logger.error().append("[input] Clearly some sort of typo");
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break;
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}
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break;
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@@ -315,7 +315,7 @@ template <Analyser::Static::Sega::Target::Model model> class ConcreteMachine:
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case 0x00: // i.e. even ports less than 0x40.
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if constexpr (is_master_system(model)) {
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// TODO: Obey the RAM enable.
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LOG("Memory control: " << PADHEX(2) << +memory_control_);
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logger.info().append("Memory control: %02x", memory_control_);
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memory_control_ = *cycle.value;
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page_cartridge();
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}
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@@ -357,7 +357,7 @@ template <Analyser::Static::Sega::Target::Model model> class ConcreteMachine:
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break;
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default:
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ERROR("[output] Clearly some sort of typo");
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logger.error().append("[output] Clearly some sort of typo");
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break;
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}
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break;
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