1
0
mirror of https://github.com/TomHarte/CLK.git synced 2024-11-23 03:32:32 +00:00

Restores proper phase with the CPU.

This commit is contained in:
Thomas Harte 2018-10-19 23:18:16 -04:00
parent 0822c96ce0
commit b61de65b43

View File

@ -76,9 +76,9 @@ Base::Base(Personality p) :
// This is definitely correct for the TMS; more research may be
// necessary for the other implemented VDPs.
read_pointer_.row = 0;
read_pointer_.column = 0;
write_pointer_.row = 0;
write_pointer_.column = 10; // i.e. 10 cycles ahead of the read pointer.
read_pointer_.column = 342 - 10; // i.e. 10 cycles behind the write pointer.
write_pointer_.row = 1;
write_pointer_.column = 0;
}
TMS9918::TMS9918(Personality p):