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https://github.com/TomHarte/CLK.git
synced 2024-11-25 16:31:42 +00:00
Move trans tests inside switch.
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parent
87d1a476a4
commit
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@ -71,13 +71,10 @@ struct MemoryController {
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template <typename IntT>
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template <typename IntT>
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bool write(uint32_t address, IntT source, InstructionSet::ARM::Mode, bool trans) {
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bool write(uint32_t address, IntT source, InstructionSet::ARM::Mode, bool trans) {
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// User mode may only _write_ to logically-mapped RAM (subject to further testing below).
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if(trans && address >= 0x200'0000) {
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return false;
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}
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switch(write_zones_[(address >> 21) & 31]) {
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switch(write_zones_[(address >> 21) & 31]) {
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case Zone::DMAAndMEMC: {
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case Zone::DMAAndMEMC: {
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if(trans) return false;
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const auto buffer_address = [](uint32_t source) -> uint32_t {
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const auto buffer_address = [](uint32_t source) -> uint32_t {
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return (source & 0x1'fffc) << 2;
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return (source & 0x1'fffc) << 2;
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};
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};
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@ -126,19 +123,23 @@ struct MemoryController {
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} break;
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} break;
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case Zone::IOControllers:
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case Zone::IOControllers:
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if(trans) return false;
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ioc_.template write<IntT>(address, source);
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ioc_.template write<IntT>(address, source);
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break;
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break;
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case Zone::VideoController:
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case Zone::VideoController:
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if(trans) return false;
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// TODO: handle byte writes correctly.
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// TODO: handle byte writes correctly.
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ioc_.video().write(source);
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ioc_.video().write(source);
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break;
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break;
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case Zone::PhysicallyMappedRAM:
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case Zone::PhysicallyMappedRAM:
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if(trans) return false;
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physical_ram<IntT>(address) = source;
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physical_ram<IntT>(address) = source;
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break;
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break;
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case Zone::AddressTranslator:
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case Zone::AddressTranslator:
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if(trans) return false;
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// printf("Translator write at %08x; replaces %08x\n", address, pages_[address & 0x7f]);
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// printf("Translator write at %08x; replaces %08x\n", address, pages_[address & 0x7f]);
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pages_[address & 0x7f] = address;
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pages_[address & 0x7f] = address;
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map_dirty_ = true;
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map_dirty_ = true;
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@ -154,13 +155,9 @@ struct MemoryController {
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template <typename IntT>
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template <typename IntT>
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bool read(uint32_t address, IntT &source, InstructionSet::ARM::Mode, bool trans) {
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bool read(uint32_t address, IntT &source, InstructionSet::ARM::Mode, bool trans) {
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// User mode may only read logically-maped RAM and ROM.
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if(trans && address >= 0x200'0000 && address < 0x380'0000) {
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return false;
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}
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switch (read_zones_[(address >> 21) & 31]) {
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switch (read_zones_[(address >> 21) & 31]) {
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case Zone::PhysicallyMappedRAM:
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case Zone::PhysicallyMappedRAM:
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if(trans) return false;
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source = physical_ram<IntT>(address);
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source = physical_ram<IntT>(address);
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break;
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break;
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@ -184,6 +181,7 @@ struct MemoryController {
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break;
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break;
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case Zone::IOControllers:
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case Zone::IOControllers:
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if(trans) return false;
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ioc_.template read<IntT>(address, source);
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ioc_.template read<IntT>(address, source);
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break;
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break;
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