From b64da2710a9bbc21dd779662285c99dc862d90de Mon Sep 17 00:00:00 2001 From: Thomas Harte Date: Wed, 17 Apr 2019 10:00:14 -0400 Subject: [PATCH] Corrects a few MOVE #s. --- OSBindings/Mac/Clock SignalTests/QLTests.mm | 7 ++++--- Processors/68000/Implementation/68000Storage.cpp | 7 ++++++- 2 files changed, 10 insertions(+), 4 deletions(-) diff --git a/OSBindings/Mac/Clock SignalTests/QLTests.mm b/OSBindings/Mac/Clock SignalTests/QLTests.mm index 35b5f0f4b..543fec25f 100644 --- a/OSBindings/Mac/Clock SignalTests/QLTests.mm +++ b/OSBindings/Mac/Clock SignalTests/QLTests.mm @@ -79,12 +79,12 @@ class QL: public CPU::MC68000::BusHandler { break; case Microcycle::SelectWord: assert(!(is_rom && !is_peripheral)); - if(!(cycle.operation & Microcycle::IsProgram)) printf("[word w %08x <- %04x] ", *cycle.address, cycle.value->full); + if(!(cycle.operation & Microcycle::IsProgram)) printf("[word w %04x -> %08x] ", cycle.value->full, *cycle.address); if(!is_peripheral) base[word_address] = cycle.value->full; break; case Microcycle::SelectByte: assert(!(is_rom && !is_peripheral)); - if(!(cycle.operation & Microcycle::IsProgram)) printf("[byte w %08x <- %02x] ", *cycle.address, (cycle.value->full >> cycle.byte_shift()) & 0xff); + if(!(cycle.operation & Microcycle::IsProgram)) printf("[byte w %02x -> %08x] ", (cycle.value->full >> cycle.byte_shift()) & 0xff, *cycle.address); if(!is_peripheral) base[word_address] = (cycle.value->full & cycle.byte_mask()) | (base[word_address] & (0xffff ^ cycle.byte_mask())); break; } @@ -115,7 +115,8 @@ class QL: public CPU::MC68000::BusHandler { - (void)testStartup { // This is an example of a functional test case. // Use XCTAssert and related functions to verify your tests produce the correct results. - _machine->run_for(HalfCycles(16000000)); + _machine->run_for(HalfCycles(40000000)); } @end + diff --git a/Processors/68000/Implementation/68000Storage.cpp b/Processors/68000/Implementation/68000Storage.cpp index 6a635f1b8..1ae496c9e 100644 --- a/Processors/68000/Implementation/68000Storage.cpp +++ b/Processors/68000/Implementation/68000Storage.cpp @@ -2413,7 +2413,8 @@ struct ProcessorStorageConstructor { case bw2(Imm, d8AnXn): // MOVE.bw #, (d8, An, Xn) case bw2(Imm, d16PC): // MOVE.bw #, (d16, PC) case bw2(Imm, d8PCXn): // MOVE.bw #, (d8, PC, Xn) - op(int(Action::AssembleWordDataFromPrefetch) | MicroOp::SourceMask, seq("np")); + storage_.instructions[instruction].source = &storage_.destination_bus_data_[0]; + op(int(Action::AssembleWordDataFromPrefetch) | MicroOp::DestinationMask, seq("np")); op(calc_action_for_mode(destination_mode) | MicroOp::DestinationMask, seq(pseq("np nw np", destination_mode), { ea(1) }, !is_byte_access )); op(is_byte_access ? Action::SetMoveFlagsb : Action::SetMoveFlagsl); break; @@ -2546,18 +2547,21 @@ struct ProcessorStorageConstructor { break; case bw2(Imm, XXXw): // MOVE.bw #, (xxx).w + storage_.instructions[instruction].source = &storage_.destination_bus_data_[0]; op(int(Action::AssembleWordDataFromPrefetch) | MicroOp::DestinationMask, seq("np")); op(int(Action::AssembleWordAddressFromPrefetch) | MicroOp::DestinationMask, seq("np nw np", { ea(1) }, !is_byte_access)); op(is_byte_access ? Action::SetMoveFlagsb : Action::SetMoveFlagsw); break; case bw2(Imm, XXXl): // MOVE.bw #, (xxx).l + storage_.instructions[instruction].source = &storage_.destination_bus_data_[0]; op(int(Action::AssembleWordDataFromPrefetch) | MicroOp::DestinationMask, seq("np np")); op(int(Action::AssembleLongWordAddressFromPrefetch) | MicroOp::DestinationMask, seq("np nw np", { ea(1) })); op(is_byte_access ? Action::SetMoveFlagsb : Action::SetMoveFlagsw); break; case l2(Imm, XXXw): // MOVE.l #, (xxx).w + storage_.instructions[instruction].source = &storage_.destination_bus_data_[0]; op(int(Action::None), seq("np")); op(int(Action::AssembleLongWordDataFromPrefetch) | MicroOp::DestinationMask, seq("np")); op(int(Action::AssembleWordAddressFromPrefetch) | MicroOp::DestinationMask, seq("np nW+ nw np", { ea(1), ea(1) })); @@ -2565,6 +2569,7 @@ struct ProcessorStorageConstructor { break; case l2(Imm, XXXl): // MOVE.l #, (xxx).l + storage_.instructions[instruction].source = &storage_.destination_bus_data_[0]; op(int(Action::None), seq("np")); op(int(Action::AssembleLongWordDataFromPrefetch) | MicroOp::DestinationMask, seq("np np")); op(int(Action::AssembleLongWordAddressFromPrefetch) | MicroOp::DestinationMask, seq("np nW+ nw np", { ea(1), ea(1) }));