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Add tests, exclusions for rest of shift/roll group.

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This commit is contained in:
Thomas Harte 2022-04-21 11:26:56 -04:00
parent d346d4a9b6
commit b6b092d124
2 changed files with 72 additions and 25 deletions
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46
InstructionSets/68k/Decoder.cpp
View File

@ -329,6 +329,22 @@ template <uint8_t op, bool validate> Preinstruction Predecoder<model>::validated
case AddressingMode::None:
return Preinstruction();
}
case OpT(Operation::ASLm): case OpT(Operation::ASRm):
case OpT(Operation::LSLm): case OpT(Operation::LSRm):
case OpT(Operation::ROLm): case OpT(Operation::RORm):
case OpT(Operation::ROXLm): case OpT(Operation::ROXRm):
switch(original.mode<0>()) {
default: return original;
case AddressingMode::DataRegisterDirect:
case AddressingMode::AddressRegisterDirect:
case AddressingMode::ImmediateData:
case AddressingMode::ProgramCounterIndirectWithDisplacement:
case AddressingMode::ProgramCounterIndirectWithIndex8bitDisplacement:
case AddressingMode::None:
return Preinstruction();
}
}
}
@ -706,8 +722,8 @@ template <uint8_t op, bool validate> Preinstruction Predecoder<model>::decode(ui
case OpT(Operation::ROLb): case OpT(Operation::ROLw): case OpT(Operation::ROLl):
return validated<op, validate>(
Preinstruction(operation,
AddressingMode::DataRegisterDirect, ea_register,
(instruction & 0x100) ? AddressingMode::DataRegisterDirect : AddressingMode::Quick, data_register));
(instruction & 0x20) ? AddressingMode::DataRegisterDirect : AddressingMode::Quick, data_register,
AddressingMode::DataRegisterDirect, ea_register));
//
// MARK: ASRm, LSRm, ROXRm, RORm, ASLm, LSLm, ROXLm, ROLm
@ -1183,6 +1199,19 @@ template <Model model>
Preinstruction Predecoder<model>::decodeE(uint16_t instruction) {
using Op = Operation;
switch(instruction & 0xfc0) {
case 0x0c0: Decode(Op::ASRm); // 4-22 (p126)
case 0x1c0: Decode(Op::ASLm); // 4-22 (p126)
case 0x2c0: Decode(Op::LSRm); // 4-113 (p217)
case 0x3c0: Decode(Op::LSLm); // 4-113 (p217)
case 0x4c0: Decode(Op::ROXRm); // 4-163 (p267)
case 0x5c0: Decode(Op::ROXLm); // 4-163 (p267)
case 0x6c0: Decode(Op::RORm); // 4-160 (p264)
case 0x7c0: Decode(Op::ROLm); // 4-160 (p264)
default: break;
}
switch(instruction & 0x1d8) {
// 4-22 (p126)
case 0x000: Decode(Op::ASRb);
@ -1227,19 +1256,6 @@ Preinstruction Predecoder<model>::decodeE(uint16_t instruction) {
default: break;
}
switch(instruction & 0xfc0) {
case 0x0c0: Decode(Op::ASRm); // 4-22 (p126)
case 0x1c0: Decode(Op::ASLm); // 4-22 (p126)
case 0x2c0: Decode(Op::LSRm); // 4-113 (p217)
case 0x3c0: Decode(Op::LSLm); // 4-113 (p217)
case 0x4c0: Decode(Op::ROXRm); // 4-163 (p267)
case 0x5c0: Decode(Op::ROXLm); // 4-163 (p267)
case 0x6c0: Decode(Op::RORm); // 4-160 (p264)
case 0x7c0: Decode(Op::ROLm); // 4-160 (p264)
default: break;
}
return Preinstruction();
}

51
OSBindings/Mac/Clock SignalTests/m68kDecoderTests.mm
View File

@ -71,6 +71,7 @@ template <int index> NSString *operand(Preinstruction instruction) {
XCTAssertNotNil(decodings);
Predecoder<Model::M68000> decoder;
int skipped = 0;
for(int instr = 0; instr < 65536; instr++) {
NSString *const instrName = [NSString stringWithFormat:@"%04x", instr];
NSString *const expected = decodings[instrName];
@ -180,18 +181,44 @@ template <int index> NSString *operand(Preinstruction instruction) {
case Operation::ASLl: instruction = @"ASL.l"; break;
case Operation::ASLm: instruction = @"ASL.w"; break;
case Operation::ASRb: instruction = @"ASR.b"; break;
case Operation::ASRw: instruction = @"ASR.w"; break;
case Operation::ASRl: instruction = @"ASR.l"; break;
case Operation::ASRm: instruction = @"ASR.w"; break;
case Operation::LSLb: instruction = @"LSL.b"; break;
case Operation::LSLw: instruction = @"LSL.w"; break;
case Operation::LSLl: instruction = @"LSL.l"; break;
case Operation::LSLm: instruction = @"LSL.w"; break;
case Operation::LSRb: instruction = @"LSR.b"; break;
case Operation::LSRw: instruction = @"LSR.w"; break;
case Operation::LSRl: instruction = @"LSR.l"; break;
case Operation::LSRm: instruction = @"LSR.w"; break;
case Operation::ROLb: instruction = @"ROL.b"; break;
case Operation::ROLw: instruction = @"ROL.w"; break;
case Operation::ROLl: instruction = @"ROL.l"; break;
case Operation::ROLm: instruction = @"ROL.w"; break;
case Operation::RORb: instruction = @"ROR.b"; break;
case Operation::RORw: instruction = @"ROR.w"; break;
case Operation::RORl: instruction = @"ROR.l"; break;
case Operation::RORm: instruction = @"ROR.w"; break;
case Operation::ROXLb: instruction = @"ROXL.b"; break;
case Operation::ROXLw: instruction = @"ROXL.w"; break;
case Operation::ROXLl: instruction = @"ROXL.l"; break;
case Operation::ROXLm: instruction = @"ROXL.w"; break;
case Operation::ROXRb: instruction = @"ROXR.b"; break;
case Operation::ROXRw: instruction = @"ROXR.w"; break;
case Operation::ROXRl: instruction = @"ROXR.l"; break;
case Operation::ROXRm: instruction = @"ROXR.w"; break;
/*
TODO:
ASLb, ASLw, ASLl, ASLm,
ASRb, ASRw, ASRl, ASRm,
LSLb, LSLw, LSLl, LSLm,
LSRb, LSRw, LSRl, LSRm,
ROLb, ROLw, ROLl, ROLm,
RORb, RORw, RORl, RORm,
ROXLb, ROXLw, ROXLl, ROXLm,
ROXRb, ROXRw, ROXRl, ROXRm,
MOVEMl, MOVEMw,
MOVEPl, MOVEPw,
@ -220,7 +247,9 @@ template <int index> NSString *operand(Preinstruction instruction) {
*/
// For now, skip any unmapped operations.
default: continue;
default:
++skipped;
continue;
}
NSString *const operand1 = operand<0>(found);
@ -231,6 +260,7 @@ template <int index> NSString *operand(Preinstruction instruction) {
// Quick decoding not yet supported. TODO.
if(found.mode<0>() == AddressingMode::Quick || found.mode<1>() == AddressingMode::Quick) {
++skipped;
continue;
}
@ -238,6 +268,7 @@ template <int index> NSString *operand(Preinstruction instruction) {
XCTAssertEqualObjects(instruction, expected, "%@ should decode as %@; got %@", instrName, expected, instruction);
}
NSLog(@"Skipped %d opcodes", skipped);
}
@end