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mirror of https://github.com/TomHarte/CLK.git synced 2024-11-25 01:32:55 +00:00

Shuffle construction order.

This commit is contained in:
Thomas Harte 2024-10-15 21:51:23 -04:00
parent f3e18da416
commit b701ce9721
2 changed files with 5 additions and 4 deletions

View File

@ -91,8 +91,8 @@ template <Analyser::Static::Macintosh::Target::Model model> class ConcreteMachin
mc68000_(*this), mc68000_(*this),
iwm_(CLOCK_RATE), iwm_(CLOCK_RATE),
video_(audio_, drive_speed_accumulator_), video_(audio_, drive_speed_accumulator_),
via_(via_port_handler_),
via_port_handler_(*this, clock_, keyboard_, audio_, iwm_, mouse_), via_port_handler_(*this, clock_, keyboard_, audio_, iwm_, mouse_),
via_(via_port_handler_),
scsi_bus_(CLOCK_RATE * 2), scsi_bus_(CLOCK_RATE * 2),
scsi_(scsi_bus_, CLOCK_RATE * 2), scsi_(scsi_bus_, CLOCK_RATE * 2),
hard_drive_(scsi_bus_, 6 /* SCSI ID */), hard_drive_(scsi_bus_, 6 /* SCSI ID */),
@ -760,8 +760,8 @@ template <Analyser::Static::Macintosh::Target::Model model> class ConcreteMachin
Apple::Clock::SerialClock clock_; Apple::Clock::SerialClock clock_;
Keyboard keyboard_; Keyboard keyboard_;
MOS::MOS6522::MOS6522<VIAPortHandler> via_;
VIAPortHandler via_port_handler_; VIAPortHandler via_port_handler_;
MOS::MOS6522::MOS6522<VIAPortHandler> via_;
Zilog::SCC::z8530 scc_; Zilog::SCC::z8530 scc_;
SCSI::Bus scsi_bus_; SCSI::Bus scsi_bus_;

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@ -198,10 +198,10 @@ class ConcreteMachine:
public: public:
ConcreteMachine(const Target &target, const ROMMachine::ROMFetcher &rom_fetcher): ConcreteMachine(const Target &target, const ROMMachine::ROMFetcher &rom_fetcher):
z80_(*this), z80_(*this),
i8255_(i8255_port_handler_),
tape_player_(3579545 * 2), tape_player_(3579545 * 2),
i8255_port_handler_(*this, speaker_.audio_toggle, tape_player_), i8255_port_handler_(*this, speaker_.audio_toggle, tape_player_),
ay_port_handler_(tape_player_), ay_port_handler_(tape_player_),
i8255_(i8255_port_handler_),
memory_slots_{{*this}, {*this}, {*this}, {*this}}, memory_slots_{{*this}, {*this}, {*this}, {*this}},
clock_(ClockRate) { clock_(ClockRate) {
set_clock_rate(ClockRate); set_clock_rate(ClockRate);
@ -913,7 +913,6 @@ class ConcreteMachine:
CPU::Z80::Processor<ConcreteMachine, false, false> z80_; CPU::Z80::Processor<ConcreteMachine, false, false> z80_;
JustInTimeActor<TI::TMS::TMS9918<vdp_model()>> vdp_; JustInTimeActor<TI::TMS::TMS9918<vdp_model()>> vdp_;
Intel::i8255::i8255<i8255PortHandler> i8255_;
Storage::Tape::BinaryTapePlayer tape_player_; Storage::Tape::BinaryTapePlayer tape_player_;
bool tape_player_is_sleeping_ = false; bool tape_player_is_sleeping_ = false;
@ -932,6 +931,8 @@ class ConcreteMachine:
Speaker<has_opll> speaker_; Speaker<has_opll> speaker_;
AYPortHandler ay_port_handler_; AYPortHandler ay_port_handler_;
Intel::i8255::i8255<i8255PortHandler> i8255_;
/// The current primary and secondary slot selections; the former retains whatever was written /// The current primary and secondary slot selections; the former retains whatever was written
/// last to the 8255 PPI via port A8 and the latter — if enabled — captures 0xffff on a per-slot basis. /// last to the 8255 PPI via port A8 and the latter — if enabled — captures 0xffff on a per-slot basis.
uint8_t primary_slots_ = 0; uint8_t primary_slots_ = 0;