From b7bed027d77dfb7c4e5f9d159bdcbdc41e19b285 Mon Sep 17 00:00:00 2001
From: Thomas Harte <thomas.harte@gmail.com>
Date: Sun, 25 Jul 2021 19:55:23 -0400
Subject: [PATCH] Ensures the value initially loaded to A7 is aligned.

This is a bit of a guess; it's likely to be true though per the rule that A7 is always kept aligned.
---
 .../68000/Implementation/68000Implementation.hpp    | 13 +++++++++++++
 Processors/68000/Implementation/68000Storage.cpp    |  2 +-
 Processors/68000/Implementation/68000Storage.hpp    |  5 +++++
 3 files changed, 19 insertions(+), 1 deletion(-)

diff --git a/Processors/68000/Implementation/68000Implementation.hpp b/Processors/68000/Implementation/68000Implementation.hpp
index 87f0aba13..53331f40f 100644
--- a/Processors/68000/Implementation/68000Implementation.hpp
+++ b/Processors/68000/Implementation/68000Implementation.hpp
@@ -191,6 +191,11 @@ template <class T, bool dtack_is_implicit, bool signal_will_perform> void Proces
 							case BusStep::Action::DecrementEffectiveAddress1:	effective_address_[1].full -= 2;	break;
 							case BusStep::Action::IncrementProgramCounter:		program_counter_.full += 2;			break;
 
+							case BusStep::Action::IncrementEffectiveAddress0AlignStackPointer:
+								effective_address_[0].full += 2;
+								address_[7].full &= 0xffff'fffe;
+							break;
+
 							case BusStep::Action::AdvancePrefetch:
 								prefetch_queue_.halves.high = prefetch_queue_.halves.low;
 
@@ -299,6 +304,14 @@ template <class T, bool dtack_is_implicit, bool signal_will_perform> void Proces
 							}
 #endif
 
+							static uint32_t last_a7 = address_[7].full;
+							log |= (program_counter_.full - 4 == 0x00fcafba);
+//							if(log) {
+							if(log && last_a7 != address_[7].full) {
+								last_a7 = address_[7].full;
+								printf("%08x a7:%08x\n", program_counter_.full - 4, address_[7].full);
+							}
+
 							decoded_instruction_.full = prefetch_queue_.halves.high.full;
 
 #ifndef NDEBUG
diff --git a/Processors/68000/Implementation/68000Storage.cpp b/Processors/68000/Implementation/68000Storage.cpp
index f3aaa0c1d..96932a669 100644
--- a/Processors/68000/Implementation/68000Storage.cpp
+++ b/Processors/68000/Implementation/68000Storage.cpp
@@ -261,7 +261,7 @@ struct ProcessorStorageConstructor {
 					steps.push_back(step);
 
 					step.microcycle.operation = Microcycle::SameAddress | Microcycle::Read | Microcycle::IsProgram | Microcycle::SelectWord;
-					step.action = Action::IncrementEffectiveAddress0;
+					step.action = isupper(access_pattern[1]) ? Action::IncrementEffectiveAddress0 : Action::IncrementEffectiveAddress0AlignStackPointer;
 					steps.push_back(step);
 
 					continue;
diff --git a/Processors/68000/Implementation/68000Storage.hpp b/Processors/68000/Implementation/68000Storage.hpp
index c37b0c339..acac57523 100644
--- a/Processors/68000/Implementation/68000Storage.hpp
+++ b/Processors/68000/Implementation/68000Storage.hpp
@@ -196,6 +196,9 @@ class ProcessorStorage {
 				/// Copies prefetch_queue_[1] to prefetch_queue_[0].
 				AdvancePrefetch,
 
+				/// Performs effective_address_[0] += 2 and zeroes the final bit of the stack pointer.
+				IncrementEffectiveAddress0AlignStackPointer,
+
 				/*!
 					Terminates an atomic program; if nothing else is pending, schedules the next instruction.
 					This action is special in that it usurps any included microcycle. So any Step with this
@@ -550,6 +553,8 @@ class ProcessorStorage {
 		inline uint16_t get_status() const;
 		inline void set_status(uint16_t);
 
+		bool log = false;
+
 	private:
 		friend struct ProcessorStorageConstructor;
 		friend class ProcessorStorageTests;