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Disallow programmatic setting of blitter status.
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07facc0636
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@ -582,12 +582,12 @@ void Chipset::perform(const CPU::MC68000::Microcycle &cycle) {
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#define Read(address) address | (Microcycle::Read << 12)
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#define Read(address) address | (Microcycle::Read << 12)
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#define Write(address) address
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#define Write(address) address
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#define ApplySetClear(target) { \
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#define ApplySetClear(target, mask) { \
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const uint16_t value = cycle.value16(); \
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const uint16_t value = cycle.value16(); \
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if(value & 0x8000) { \
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if(value & 0x8000) { \
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target |= (value & 0x7fff); \
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target |= (value & mask); \
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} else { \
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} else { \
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target &= ~(value & 0x7fff); \
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target &= ~(value & mask); \
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} \
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} \
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}
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}
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@ -642,7 +642,7 @@ void Chipset::perform(const CPU::MC68000::Microcycle &cycle) {
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case Write(0x09e):
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case Write(0x09e):
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LOG("Write disk control");
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LOG("Write disk control");
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ApplySetClear(paula_disk_control_);
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ApplySetClear(paula_disk_control_, 0x7fff);
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disk_controller_.set_control(paula_disk_control_);
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disk_controller_.set_control(paula_disk_control_);
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// TODO: should also post to Paula.
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// TODO: should also post to Paula.
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@ -684,12 +684,12 @@ void Chipset::perform(const CPU::MC68000::Microcycle &cycle) {
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cycle.set_value16(dma_control_ | blitter_.get_status());
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cycle.set_value16(dma_control_ | blitter_.get_status());
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break;
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break;
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case Write(0x096):
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case Write(0x096):
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ApplySetClear(dma_control_);
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ApplySetClear(dma_control_, 0x1fff);
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break;
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break;
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// Interrupts.
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// Interrupts.
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case Write(0x09a):
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case Write(0x09a):
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ApplySetClear(interrupt_enable_);
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ApplySetClear(interrupt_enable_, 0x7fff);
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update_interrupts();
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update_interrupts();
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break;
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break;
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case Read(0x01c):
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case Read(0x01c):
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@ -697,7 +697,7 @@ void Chipset::perform(const CPU::MC68000::Microcycle &cycle) {
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break;
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break;
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case Write(0x09c):
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case Write(0x09c):
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ApplySetClear(interrupt_requests_);
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ApplySetClear(interrupt_requests_, 0x7fff);
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update_interrupts();
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update_interrupts();
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break;
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break;
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case Read(0x01e):
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case Read(0x01e):
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