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Merge branch 'PowerPCTests' of github.com:TomHarte/CLK into PowerPCTests
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Thomas Harte
commit
b9c8016aca
@ -64,19 +64,31 @@ enum class Operation: uint8_t {
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Undefined,
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//
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// These 601-exclusive instructions; a lot of them are carry-overs
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// from POWER. These are not part of the PowerPC architecture.
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// MARK: - 601-exclusive instructions.
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//
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// A lot of them are carry-overs from POWER, left in place
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// due to the tight original development timeline.
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//
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// These are not part of the PowerPC architecture.
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/// Absolute.
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/// abs, abs., abso, abso.
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///
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/// |rA| is placed into rD. If rA = 0x8000'0000 then 0x8000'0000 is placed into rD
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/// and XER[OV] is set if oe() indicates that overflow is enabled.
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absx,
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/// Cache line compute size.
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/// clcs
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///
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/// The size of the cache line specified by rA is placed into rD. Cf. the CacheLine enum.
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/// As an aside: all cache lines are 64 bytes on the MPC601.
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clcs,
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/// div, div., divo, div.; unsigned 64-bit divide. rA|MQ / rB is placed into rD and the
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/// Divide.
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/// div, div., divo, divo.
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///
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/// Unsigned 64-bit divide. rA|MQ / rB is placed into rD and the
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/// remainder is placed into MQ. The ermainder has the same sign as the dividend
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/// such that remainder + divisor * quotient = dividend.
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///
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@ -84,7 +96,10 @@ enum class Operation: uint8_t {
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/// oe() != 0 => SO and OV are set if the quotient exceeds 32 bits.
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divx,
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/// divs, divs., divso, divso.; signed 32-bit divide. rD = rA/rB; remainder is
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/// Divide short.
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/// divs, divs., divso, divso.
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///
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/// Signed 32-bit divide. rD = rA/rB; remainder is
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/// placed into MQ. The ermainder has the same sign as the dividend
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/// such that remainder + divisor * quotient = dividend.
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///
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@ -92,9 +107,15 @@ enum class Operation: uint8_t {
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/// oe() != 0 => SO and OV are set if the quotient exceeds 32 bits.
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divsx,
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/// Difference or zero.
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/// dozi
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///
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/// if rA > rB then rD = 0; else rD = NOT(rA) + rB + 1.
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dozx,
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/// Difference or zero immediate.
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/// dozi
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///
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/// if rA > simm() then rD = 0; else rD = NOT(rA) + simm() + 1.
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dozi,
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@ -103,63 +124,92 @@ enum class Operation: uint8_t {
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sraiqx, sraqx, srex, sreax, sreqx, sriqx, srliqx, srlqx, srqx,
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//
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// 32- and 64-bit PowerPC instructions.
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// MARK: - 32- and 64-bit PowerPC instructions.
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//
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addx, addcx, addex,
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/// Add.
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/// add, add., addo, addo.
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///
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/// rD() = rA() + rB(). Carry is ignored, rD() may be equal to rA() or rB().
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addx,
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/// Add carrying.
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/// addc. addc., addco, addco.
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///
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/// rD() = rA() + rB(). XER[CA] is set if a carry occurs.
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/// oe() and rc() apply.
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addcx,
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/// Add extended.
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/// adde, adde., addeo, addeo.
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///
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/// rD() = rA() + rB() + XER[CA]; XER[CA] is set if further carry occurs.
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/// oe() and rc() apply.
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addex,
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/// Add immediate.
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/// addi
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///
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/// rD() = (rA() | 0) + simm()
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addi,
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/// Add immediate carrying.
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/// addic
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///
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/// rD() = (rA() | 0) + simm()
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/// XER[CA] = carry.
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/// XER[CA] is updated.
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addic,
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/// Add immediate carrying.
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/// Add immediate carrying and record.
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/// addic.
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///
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/// rD() = (rA() | 0) + simm()
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/// XER[CA] = carry, and the condition register is updated.
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/// XER[CA] and the condition register are updated.
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addic_,
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/// Add immediate shifter.
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/// Add immediate shifted.
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/// addis.
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///
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/// rD() = (rA() | 0) + (simm() << 16)
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addis,
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addmex, addzex, andx,
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andcx, andi_, andis_,
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/// Add to minus one.
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/// addme, addme., addmeo, addmeo.
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///
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/// rD() = rA() + XER[CA] + 0xffff'ffff
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/// oe() and rc() apply.
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addmex,
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/// Add to zero extended.
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/// addze, addze., addzeo, addzeo.
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///
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/// rD() = rA() + XER[CA]
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/// oe() and rc() apply.
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addzex,
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andx, andcx, andi_, andis_,
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/// Branch unconditional.
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/// b, bl, ba, bla
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///
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/// Use li() to get the included immediate value.
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///
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/// Use aa() to determine whether it's a relative (aa() = 0) or absolute (aa() != 0) address.
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/// Also check lk() to determine whether to update the link register.
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///
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/// Synonyms include:
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/// * b (relative, no link) [though assemblers might encode as a bcx];
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/// * bl (relative, link);
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/// * ba (absolute, no link);
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/// * bla (absolute, link).
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bx,
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/// Branch conditional.
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/// bne, bne+, beq, bdnzt+, bdnzf, bdnzt, bdnzfla ...
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///
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/// aa() determines whether the branch has a relative or absolute target.
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/// lk() determines whether to update the link register.
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/// bd() supplies a relative displacment or absolute address.
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/// bi() specifies which CR bit to use as a condition; cf. the Condition enum.
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/// bo() provides other branch options and a branch prediction hint as per (BranchOptions enum << 1) | hint.
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///
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/// Synonyms incude:
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/// * b (relative, no link) [though assemblers might encode as a bx].
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bcx,
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/// Branch conditional to count register.
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/// bctr, bctrl, bnectrl, bnectrl, bltctr, blectr ...
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///
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/// aa(), bi(), bo() and lk() are as per bcx.
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///
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@ -168,6 +218,7 @@ enum class Operation: uint8_t {
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bcctrx,
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/// Branch conditional to link register.
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/// blr, blrl, bltlr, blelrl, bnelrl ...
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///
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/// aa(), bi(), bo() and lk() are as per bcx.
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bclrx,
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@ -181,6 +232,7 @@ enum class Operation: uint8_t {
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icbi, isync, lbz, lbzu,
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/// Load byte and zero with update indexed.
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/// lbzux
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///
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/// rD()[24, 31] = [ rA()|0 + rB() ]; and rA() is set to the calculated address
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/// i.e. if rA() is 0 then the value 0 is used, not the contents of r0.
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@ -191,6 +243,7 @@ enum class Operation: uint8_t {
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lbzux,
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/// Load byte and zero indexed.
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/// lbzx
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///
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/// rD[24, 31] = [ (rA()|0) + rB() ]
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/// i.e. if rA() is 0 then the value 0 is used, not the contents of r0.
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@ -240,6 +293,7 @@ enum class Operation: uint8_t {
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lswi, lswx, lwarx, lwbrx, lwz, lwzu,
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/// Load word and zero with update indexed.
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/// lwzux
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///
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/// rD() = [ rA()|0 + rB() ]; and rA() is set to the calculated address
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/// i.e. if rA() is 0 then the value 0 is used, not the contents of r0.
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@ -249,6 +303,7 @@ enum class Operation: uint8_t {
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lwzux,
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/// Load word and zero indexed.
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/// lwzx
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///
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/// rD() = [ (rA()|0) + rB() ]
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/// i.e. if rA() is 0 then the value 0 is used, not the contents of r0.
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@ -333,17 +388,23 @@ enum class Operation: uint8_t {
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subfmex, subfzex, sync, tw, twi, xorx, xori, xoris, mftb,
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// 32-bit, supervisor level.
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//
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// MARK: - 32-bit, supervisor level.
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//
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dcbi,
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// Supervisor, optional.
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//
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// MARK: - Supervisor, optional.
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//
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tlbia, tlbie, tlbsync,
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// Optional.
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//
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// MARK: - Optional.
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//
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fresx, frsqrtex, fselx, fsqrtx, slbia, slbie, stfiwx,
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//
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// 64-bit only PowerPC instructions.
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// MARK: - 64-bit only PowerPC instructions.
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//
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cntlzdx, divdx, divdux, extswx, fcfidx, fctidx, fctidzx, tdi, mulhdux,
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ldx, sldx, ldux, td, mulhdx, ldarx, stdx, stdux, mulld, lwax, lwaux,
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