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https://github.com/TomHarte/CLK.git
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Merge pull request #163 from TomHarte/WaitSampling
Adjusts the timing of the Z80's wait line sampling to be on a half clock and better regularises 'action' partial bus cycles
This commit is contained in:
Thomas Harte
GitHub
commit
b9f4f7a530
@ -99,8 +99,12 @@ HalfCycles Machine::perform_machine_cycle(const CPU::Z80::PartialMachineCycle &c
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} break;
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case CPU::Z80::PartialMachineCycle::Interrupt:
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// resetting event is M1 and IOREQ both simultaneously having leading edges;
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// that happens 2 cycles before the end of INTACK. So the timer was reset and
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// now has advanced twice.
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horizontal_counter_ = HalfCycles(2);
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*cycle.value = 0xff;
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horizontal_counter_ = 0;
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break;
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case CPU::Z80::PartialMachineCycle::Refresh:
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@ -109,7 +113,7 @@ HalfCycles Machine::perform_machine_cycle(const CPU::Z80::PartialMachineCycle &c
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// final two cycles of an opcode fetch. Therefore communicate a transient signalling
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// of the IRQ line if necessary.
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if(!(address & 0x40)) {
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set_interrupt_line(true, -2);
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set_interrupt_line(true, Cycles(-2));
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set_interrupt_line(false);
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}
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if(has_latched_video_byte_) {
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@ -126,8 +130,7 @@ HalfCycles Machine::perform_machine_cycle(const CPU::Z80::PartialMachineCycle &c
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}
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break;
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case CPU::Z80::PartialMachineCycle::ReadOpcodeStart:
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case CPU::Z80::PartialMachineCycle::ReadOpcodeWait:
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case CPU::Z80::PartialMachineCycle::ReadOpcode:
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// Check for use of the fast tape hack.
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if(use_fast_tape_hack_ && address == tape_trap_address_ && tape_player_.has_tape()) {
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uint64_t prior_offset = tape_player_.get_tape()->get_offset();
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@ -34,6 +34,7 @@ class MOS6502TimingTests: XCTestCase, CSTestMachineTrapHandler {
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0xbd, 0x00, 0x00, // [4] LDA $0000, x (no wrap)
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0xbd, 0x02, 0x00, // [5] LDA $0002, x (wrap)
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0xb9, 0x00, 0x00, // [4] LDA $0000, y (no wrap)
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0xb9, 0x10, 0x00, // [5] LDA $0010, y (wrap)
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0xa1, 0x44, // [6] LDA ($44, x)
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0xb1, 0x00, // [5] LDA ($00), y (no wrap)
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@ -222,7 +223,7 @@ class MOS6502TimingTests: XCTestCase, CSTestMachineTrapHandler {
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func testMachine(_ testMachine: CSTestMachine, didTrapAtAddress address: UInt16) {
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if self.endTime == 0 {
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self.endTime = machine.timestamp - 1
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self.endTime = (machine.timestamp / 2) - 1
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}
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}
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}
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@ -78,7 +78,7 @@ static CPU::MOS6502::Register registerForRegister(CSTestMachine6502Register reg)
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}
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- (uint32_t)timestamp {
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return _processor->get_timestamp();
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return _processor->get_timestamp().as_int();
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}
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- (void)setIrqLine:(BOOL)irqLine {
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@ -61,7 +61,7 @@ typedef NS_ENUM(NSInteger, CSTestMachineZ80Register) {
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@property(nonatomic, readonly, nonnull) NSArray<CSTestMachineZ80BusOperationCapture *> *busOperationCaptures;
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@property(nonatomic, readonly) BOOL isHalted;
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@property(nonatomic, readonly) int completedCycles;
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@property(nonatomic, readonly) int completedHalfCycles;
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@property(nonatomic) BOOL nmiLine;
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@property(nonatomic) BOOL irqLine;
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@ -14,7 +14,7 @@
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- (void)testMachineDidPerformBusOperation:(CPU::Z80::PartialMachineCycle::Operation)operation
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address:(uint16_t)address
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value:(uint8_t)value
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timeStamp:(int)time_stamp;
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timeStamp:(HalfCycles)time_stamp;
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@end
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#pragma mark - C++ delegate handlers
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@ -23,7 +23,7 @@ class BusOperationHandler: public CPU::Z80::AllRAMProcessor::MemoryAccessDelegat
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public:
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BusOperationHandler(CSTestMachineZ80 *targetMachine) : target_(targetMachine) {}
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void z80_all_ram_processor_did_perform_bus_operation(CPU::Z80::AllRAMProcessor &processor, CPU::Z80::PartialMachineCycle::Operation operation, uint16_t address, uint8_t value, int time_stamp) {
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void z80_all_ram_processor_did_perform_bus_operation(CPU::Z80::AllRAMProcessor &processor, CPU::Z80::PartialMachineCycle::Operation operation, uint16_t address, uint8_t value, HalfCycles time_stamp) {
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[target_ testMachineDidPerformBusOperation:operation address:address value:value timeStamp:time_stamp];
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}
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@ -154,8 +154,8 @@ static CPU::Z80::Register registerForRegister(CSTestMachineZ80Register reg) {
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return _processor->get_halt_line() ? YES : NO;
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}
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- (int)completedCycles {
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return _processor->get_timestamp();
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- (int)completedHalfCycles {
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return _processor->get_timestamp().as_int();
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}
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- (void)setNmiLine:(BOOL)nmiLine {
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@ -184,7 +184,7 @@ static CPU::Z80::Register registerForRegister(CSTestMachineZ80Register reg) {
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_processor->set_memory_access_delegate(captureBusActivity ? _busOperationHandler : nullptr);
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}
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- (void)testMachineDidPerformBusOperation:(CPU::Z80::PartialMachineCycle::Operation)operation address:(uint16_t)address value:(uint8_t)value timeStamp:(int)timeStamp {
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- (void)testMachineDidPerformBusOperation:(CPU::Z80::PartialMachineCycle::Operation)operation address:(uint16_t)address value:(uint8_t)value timeStamp:(HalfCycles)timeStamp {
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if(self.captureBusActivity) {
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CSTestMachineZ80BusOperationCapture *capture = [[CSTestMachineZ80BusOperationCapture alloc] init];
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switch(operation) {
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@ -216,7 +216,7 @@ static CPU::Z80::Register registerForRegister(CSTestMachineZ80Register reg) {
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}
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capture.address = address;
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capture.value = value;
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capture.timeStamp = timeStamp;
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capture.timeStamp = timeStamp.as_int();
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[_busOperationCaptures addObject:capture];
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}
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@ -195,8 +195,8 @@ class FUSETests: XCTestCase {
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machine.runForNumber(ofCycles: Int32(targetState.tStates))
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// Verify that exactly the right number of cycles was hit; this is a primitive cycle length tester.
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let cyclesRun = machine.completedCycles
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XCTAssert(cyclesRun == Int32(targetState.tStates), "Instruction length off; was \(machine.completedCycles) but should be \(targetState.tStates): \(name)")
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let halfCyclesRun = machine.completedHalfCycles
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XCTAssert(halfCyclesRun == Int32(targetState.tStates) * 2, "Instruction length off; was \(machine.completedHalfCycles) but should be \(targetState.tStates * 2): \(name)")
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let finalState = RegisterState(machine: machine)
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@ -61,7 +61,9 @@ class Z80MachineCycleTests: XCTestCase {
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// array access
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break
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} else {
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if length != busCycles[index].length || cycle.operation != busCycles[index].operation {
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XCTAssert(length & Int32(1) == 0, "While performing \(machine.busOperationCaptures) Z80 ended on a half cycle")
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if length != busCycles[index].length*2 || cycle.operation != busCycles[index].operation {
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matches = false
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break;
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}
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@ -21,7 +21,7 @@ class ConcreteAllRAMProcessor: public AllRAMProcessor, public Processor<Concrete
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}
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inline Cycles perform_bus_operation(BusOperation operation, uint16_t address, uint8_t *value) {
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timestamp_++;
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timestamp_ += Cycles(1);
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if(operation == BusOperation::ReadOpcode) {
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check_address_for_trap(address);
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@ -25,7 +25,7 @@ void AllRAMProcessor::get_data_at_address(uint16_t startAddress, size_t length,
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memcpy(data, &memory_[startAddress], endAddress - startAddress);
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}
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uint32_t AllRAMProcessor::get_timestamp() {
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HalfCycles AllRAMProcessor::get_timestamp() {
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return timestamp_;
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}
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@ -13,12 +13,14 @@
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#include <set>
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#include <vector>
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#include "../ClockReceiver/ClockReceiver.hpp"
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namespace CPU {
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class AllRAMProcessor {
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public:
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AllRAMProcessor(size_t memory_size);
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virtual uint32_t get_timestamp();
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HalfCycles get_timestamp();
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void set_data_at_address(uint16_t startAddress, size_t length, const uint8_t *data);
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void get_data_at_address(uint16_t startAddress, size_t length, uint8_t *data);
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@ -31,7 +33,7 @@ class AllRAMProcessor {
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protected:
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std::vector<uint8_t> memory_;
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uint32_t timestamp_;
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HalfCycles timestamp_;
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inline void check_address_for_trap(uint16_t address) {
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if(traps_[address]) {
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@ -67,8 +67,7 @@ enum Flag: uint8_t {
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*/
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struct PartialMachineCycle {
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enum Operation {
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ReadOpcodeStart = 0,
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ReadOpcodeWait,
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ReadOpcode = 0,
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Read,
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Write,
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Input,
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@ -79,16 +78,19 @@ struct PartialMachineCycle {
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Internal,
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BusAcknowledge,
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ReadOpcodeWait,
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ReadWait,
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WriteWait,
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InputWait,
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OutputWait,
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InterruptWait,
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ReadOpcodeStart,
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ReadStart,
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WriteStart,
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InputStart,
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OutputStart,
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InterruptStart,
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} operation;
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HalfCycles length;
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uint16_t *address;
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@ -102,33 +104,37 @@ struct PartialMachineCycle {
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return operation <= Operation::BusAcknowledge;
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}
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inline bool is_wait() const {
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return operation >= Operation::ReadWait && operation <= Operation::InterruptWait;
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return operation >= Operation::ReadOpcodeWait && operation <= Operation::InterruptWait;
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}
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};
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// Elemental bus operations
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#define ReadOpcodeStart() {PartialMachineCycle::ReadOpcodeStart, HalfCycles(4), &pc_.full, &operation_, false}
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#define ReadOpcodeStart() {PartialMachineCycle::ReadOpcodeStart, HalfCycles(3), &pc_.full, &operation_, false}
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#define ReadOpcodeWait(f) {PartialMachineCycle::ReadOpcodeWait, HalfCycles(2), &pc_.full, &operation_, f}
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#define ReadOpcodeEnd() {PartialMachineCycle::ReadOpcode, HalfCycles(1), &pc_.full, &operation_, false}
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#define Refresh(len) {PartialMachineCycle::Refresh, HalfCycles(len), &refresh_addr_.full, nullptr, false}
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#define ReadStart(addr, val) {PartialMachineCycle::ReadStart, HalfCycles(4), &addr.full, &val, false}
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#define ReadStart(addr, val) {PartialMachineCycle::ReadStart, HalfCycles(3), &addr.full, &val, false}
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#define ReadWait(l, addr, val, f) {PartialMachineCycle::ReadWait, HalfCycles(l), &addr.full, &val, f}
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#define ReadEnd(addr, val) {PartialMachineCycle::Read, HalfCycles(2), &addr.full, &val, false}
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#define ReadEnd(addr, val) {PartialMachineCycle::Read, HalfCycles(3), &addr.full, &val, false}
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#define WriteStart(addr, val) {PartialMachineCycle::WriteStart,HalfCycles(4), &addr.full, &val, false}
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#define WriteStart(addr, val) {PartialMachineCycle::WriteStart,HalfCycles(3), &addr.full, &val, false}
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#define WriteWait(l, addr, val, f) {PartialMachineCycle::WriteWait, HalfCycles(l), &addr.full, &val, f}
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#define WriteEnd(addr, val) {PartialMachineCycle::Write, HalfCycles(2), &addr.full, &val, false}
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#define WriteEnd(addr, val) {PartialMachineCycle::Write, HalfCycles(3), &addr.full, &val, false}
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#define InputStart(addr, val) {PartialMachineCycle::InputStart, HalfCycles(4), &addr.full, &val, false}
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#define InputStart(addr, val) {PartialMachineCycle::InputStart, HalfCycles(3), &addr.full, &val, false}
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#define InputWait(addr, val, f) {PartialMachineCycle::InputWait, HalfCycles(2), &addr.full, &val, f}
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#define InputEnd(addr, val) {PartialMachineCycle::Input, HalfCycles(2), &addr.full, &val, false}
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#define InputEnd(addr, val) {PartialMachineCycle::Input, HalfCycles(3), &addr.full, &val, false}
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#define OutputStart(addr, val) {PartialMachineCycle::OutputStart, HalfCycles(4), &addr.full, &val, false}
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#define OutputStart(addr, val) {PartialMachineCycle::OutputStart, HalfCycles(3), &addr.full, &val, false}
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#define OutputWait(addr, val, f) {PartialMachineCycle::OutputWait, HalfCycles(2), &addr.full, &val, f}
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#define OutputEnd(addr, val) {PartialMachineCycle::Output, HalfCycles(2), &addr.full, &val, false}
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#define OutputEnd(addr, val) {PartialMachineCycle::Output, HalfCycles(3), &addr.full, &val, false}
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#define IntAck(length, val) {PartialMachineCycle::Interrupt, HalfCycles(length), nullptr, &val, false}
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#define IntAckStart(length, val) {PartialMachineCycle::InterruptStart, HalfCycles(length), nullptr, &val, false}
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#define IntWait(val) {PartialMachineCycle::InterruptWait, HalfCycles(2), nullptr, &val, true}
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#define IntAckEnd(val) {PartialMachineCycle::Interrupt, HalfCycles(3), nullptr, &val, false}
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// A wrapper to express a bus operation as a micro-op
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#define BusOp(op) {MicroOp::BusOperation, nullptr, nullptr, op}
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@ -741,12 +747,14 @@ template <class T> class Processor {
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const MicroOp normal_fetch_decode_execute[] = {
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BusOp(ReadOpcodeStart()),
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BusOp(ReadOpcodeWait(true)),
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BusOp(ReadOpcodeEnd()),
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{ MicroOp::DecodeOperation }
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};
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const MicroOp short_fetch_decode_execute[] = {
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BusOp(ReadOpcodeStart()),
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BusOp(ReadOpcodeWait(false)),
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BusOp(ReadOpcodeWait(true)),
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BusOp(ReadOpcodeEnd()),
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{ MicroOp::DecodeOperation }
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};
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copy_program((length == 4) ? normal_fetch_decode_execute : short_fetch_decode_execute, target.fetch_decode_execute);
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@ -813,6 +821,7 @@ template <class T> class Processor {
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{ MicroOp::BeginNMI },
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BusOp(ReadOpcodeStart()),
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BusOp(ReadOpcodeWait(true)),
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BusOp(ReadOpcodeEnd()),
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BusOp(Refresh(6)),
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Push(pc_),
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{ MicroOp::JumpTo66, nullptr, nullptr},
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@ -820,14 +829,16 @@ template <class T> class Processor {
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};
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MicroOp irq_mode0_program[] = {
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{ MicroOp::BeginIRQMode0 },
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BusOp(IntAck(8, operation_)),
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BusOp(IntAckStart(5, operation_)),
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BusOp(IntWait(operation_)),
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BusOp(IntAckEnd(operation_)),
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{ MicroOp::DecodeOperationNoRChange }
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};
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MicroOp irq_mode1_program[] = {
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{ MicroOp::BeginIRQ },
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BusOp(IntAck(10, operation_)),
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BusOp(IntAckStart(7, operation_)),
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BusOp(IntWait(operation_)),
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BusOp(IntAckEnd(operation_)),
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BusOp(Refresh(4)),
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Push(pc_),
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{ MicroOp::Move16, &temp16_.full, &pc_.full },
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@ -835,8 +846,9 @@ template <class T> class Processor {
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};
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MicroOp irq_mode2_program[] = {
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{ MicroOp::BeginIRQ },
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BusOp(IntAck(10, temp16_.bytes.low)),
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BusOp(IntAckStart(7, temp16_.bytes.low)),
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BusOp(IntWait(temp16_.bytes.low)),
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BusOp(IntAckEnd(temp16_.bytes.low)),
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BusOp(Refresh(4)),
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Push(pc_),
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{ MicroOp::Move8, &ir_.bytes.high, &temp16_.bytes.high },
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@ -1882,7 +1894,7 @@ template <class T> class Processor {
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how many cycles before now the line changed state. The value may not be longer than the
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current machine cycle. If called at any other time, this must be zero.
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*/
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void set_interrupt_line(bool value, int offset = 0) {
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void set_interrupt_line(bool value, HalfCycles offset = 0) {
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if(irq_line_ == value) return;
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// IRQ requests are level triggered and masked.
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@ -1896,7 +1908,7 @@ template <class T> class Processor {
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// If this change happened at least one cycle ago then: (i) we're promised that this is a machine
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// cycle per the contract on supplying an offset; and (ii) that means it happened before the lines
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// were sampled. So adjust the most recent sample.
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if(offset < 0) {
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if(offset <= HalfCycles(-2)) {
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last_request_status_ = (last_request_status_ & ~Interrupt::IRQ) | (request_status_ & Interrupt::IRQ);
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}
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}
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@ -17,14 +17,14 @@ class ConcreteAllRAMProcessor: public AllRAMProcessor, public Processor<Concrete
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ConcreteAllRAMProcessor() : AllRAMProcessor() {}
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inline Cycles perform_machine_cycle(const PartialMachineCycle &cycle) {
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timestamp_ += cycle.length.as_int();
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timestamp_ += cycle.length;
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if(!cycle.is_terminal()) {
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return Cycles(0);
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}
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uint16_t address = cycle.address ? *cycle.address : 0x0000;
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switch(cycle.operation) {
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case PartialMachineCycle::ReadOpcodeStart:
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case PartialMachineCycle::ReadOpcode:
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check_address_for_trap(address);
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case PartialMachineCycle::Read:
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*cycle.value = memory_[address];
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@ -57,7 +57,7 @@ class ConcreteAllRAMProcessor: public AllRAMProcessor, public Processor<Concrete
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}
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if(delegate_ != nullptr) {
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delegate_->z80_all_ram_processor_did_perform_bus_operation(*this, cycle.operation, address, cycle.value ? *cycle.value : 0x00, timestamp_ >> 1);
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delegate_->z80_all_ram_processor_did_perform_bus_operation(*this, cycle.operation, address, cycle.value ? *cycle.value : 0x00, timestamp_);
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}
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return Cycles(0);
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@ -94,10 +94,6 @@ class ConcreteAllRAMProcessor: public AllRAMProcessor, public Processor<Concrete
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void set_wait_line(bool value) {
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CPU::Z80::Processor<ConcreteAllRAMProcessor>::set_wait_line(value);
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}
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uint32_t get_timestamp() {
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return timestamp_ >> 1;
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}
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};
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}
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@ -22,7 +22,7 @@ class AllRAMProcessor:
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static AllRAMProcessor *Processor();
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struct MemoryAccessDelegate {
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virtual void z80_all_ram_processor_did_perform_bus_operation(CPU::Z80::AllRAMProcessor &processor, CPU::Z80::PartialMachineCycle::Operation operation, uint16_t address, uint8_t value, int time_stamp) = 0;
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virtual void z80_all_ram_processor_did_perform_bus_operation(CPU::Z80::AllRAMProcessor &processor, CPU::Z80::PartialMachineCycle::Operation operation, uint16_t address, uint8_t value, HalfCycles time_stamp) = 0;
|
||||
};
|
||||
inline void set_memory_access_delegate(MemoryAccessDelegate *delegate) {
|
||||
delegate_ = delegate;
|
||||
@ -38,8 +38,6 @@ class AllRAMProcessor:
|
||||
virtual void set_non_maskable_interrupt_line(bool value) = 0;
|
||||
virtual void set_wait_line(bool value) = 0;
|
||||
|
||||
virtual uint32_t get_timestamp() = 0;
|
||||
|
||||
protected:
|
||||
MemoryAccessDelegate *delegate_;
|
||||
AllRAMProcessor() : ::CPU::AllRAMProcessor(65536), delegate_(nullptr) {}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user