6502/CLK
1
0
Fork 0
mirror of https://github.com/TomHarte/CLK.git synced 2026-04-21 17:16:44 +00:00
Code Issues Projects Releases Wiki Activity

Introduces extra delays to VRAM access.

Browse Source
This commit is contained in:
Thomas Harte
2018-10-26 20:19:08 -04:00
parent 05a5c7120e
commit bb09762029
2 changed files with 24 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files
Components/9918/Implementation/9918Base.hpp
+14 -2
View File
@@ -36,7 +36,7 @@ enum class TVStandard {
NTSC
};
#define is_sega_vdp(x) x >= SMSVDP
#define is_sega_vdp(x) ((x) >= SMSVDP)
class Base {
public:
@@ -91,6 +91,14 @@ class Base {
enum class MemoryAccess {
Read, Write, None
} queued_access_ = MemoryAccess::None;
int cycles_until_access_ = 0;
int minimum_access_column_ = 0;
int vram_access_delay() {
// The Sega VDP seems to allow slightly quicker access;
// Sega types generally claim 26 Z80 cycles are sufficient.
// The received wisdom in MSX land is that it's 27.
return is_sega_vdp(personality_) ? 7 : 8;
}
// Holds the main status register.
uint8_t status_ = 0;
@@ -328,7 +336,11 @@ class Base {
}
void do_external_slot(int access_column) {
// TODO: is queued access ready yet?
// Don't do anything if the required time for the access to become executable
// has yet to pass.
if(access_column < minimum_access_column_) {
return;
}
switch(queued_access_) {
default: return;