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Corrects byte increment/decrement actions for A7.
This commit is contained in:
Thomas Harte
parent
11bf706aa2
commit
bb9424d944
@ -76,13 +76,17 @@ struct ProcessorStorageConstructor {
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return int(((mode & 0xff) == XXXw) ? Action::AssembleWordDataFromPrefetch : Action::AssembleLongWordDataFromPrefetch);
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}
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int increment_action(bool is_long_word_access, bool is_byte_access) const {
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int increment_action(bool is_long_word_access, bool is_byte_access, int reg) const {
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using Action = ProcessorBase::MicroOp::Action;
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// Special case: stack pointer byte accesses adjust by two. Cf. http://www.scarpaz.com/Attic/Didattica/Scarpazza-2005-68k-1-addressing.pdf
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if(reg == 7 && is_byte_access) return int(Action::Increment2);
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return int(is_long_word_access ? Action::Increment4 : (is_byte_access ? Action::Increment1 : Action::Increment2));
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}
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int decrement_action(bool is_long_word_access, bool is_byte_access) const {
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int decrement_action(bool is_long_word_access, bool is_byte_access, int reg) const {
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using Action = ProcessorBase::MicroOp::Action;
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// Special case: stack pointer byte accesses adjust by two. Ibid.
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if(reg == 7 && is_byte_access) return int(Action::Decrement2);
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return int(is_long_word_access ? Action::Decrement4 : (is_byte_access ? Action::Decrement1 : Action::Decrement2));
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}
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@ -652,12 +656,9 @@ struct ProcessorStorageConstructor {
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// by the few deviations.
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bool is_byte_access = (op_mode&3) == 0;
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bool is_long_word_access = (op_mode&3) == 2;
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int dec = decrement_action(is_long_word_access, is_byte_access);
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int inc = increment_action(is_long_word_access, is_byte_access);
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if(instruction == 0x4eda) {
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printf("");
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}
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#define dec(n) decrement_action(is_long_word_access, is_byte_access, n)
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#define inc(n) increment_action(is_long_word_access, is_byte_access, n)
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switch(mapping.decoder) {
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case Decoder::SWAP: {
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@ -733,12 +734,12 @@ struct ProcessorStorageConstructor {
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op(Action::None, seq("nr", { a(ea_register) }, !is_byte_access));
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op(Action::PerformOperation, seq("np nw", { a(ea_register) }, !is_byte_access));
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if(mode == PostInc) {
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op(int(is_byte_access ? Action::Increment1 : Action::Increment2) | MicroOp::DestinationMask);
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op(inc(ea_register) | MicroOp::DestinationMask);
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}
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break;
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case bw(PreDec): // [AND/OR/EOR].bw Dn, -(An)
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op(int(is_byte_access ? Action::Decrement1 : Action::Decrement2) | MicroOp::SourceMask, seq("n nrd", { a(ea_register) }, !is_byte_access));
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op(dec(ea_register) | MicroOp::SourceMask, seq("n nrd", { a(ea_register) }, !is_byte_access));
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op(Action::PerformOperation, seq("np nw", { a(ea_register) }, !is_byte_access));
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break;
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@ -802,12 +803,12 @@ struct ProcessorStorageConstructor {
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op(Action::None, seq("nr", { a(ea_register) }, !is_byte_access));
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op(Action::PerformOperation, seq("np"));
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if(mode == PostInc) {
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op(int(is_byte_access ? Action::Increment1 : Action::Increment2) | MicroOp::SourceMask);
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op(inc(ea_register) | MicroOp::SourceMask);
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}
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break;
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case bw(PreDec): // [AND/OR].bw -(An), Dn
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op(int(is_byte_access ? Action::Decrement1 : Action::Decrement2) | MicroOp::SourceMask, seq("n nr", { a(ea_register) }, !is_byte_access));
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op(dec(ea_register) | MicroOp::SourceMask, seq("n nr", { a(ea_register) }, !is_byte_access));
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op(Action::PerformOperation, seq("np"));
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break;
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@ -950,7 +951,7 @@ struct ProcessorStorageConstructor {
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seq("np nrd np", { a(ea_register) }, !is_byte_access));
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op(Action::PerformOperation, seq("nw", { a(ea_register) }, !is_byte_access));
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if(mode == PostInc) {
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op(int(is_byte_access ? Action::Increment1 : Action::Increment2) | MicroOp::DestinationMask);
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op(inc(ea_register) | MicroOp::DestinationMask);
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}
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break;
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@ -966,7 +967,7 @@ struct ProcessorStorageConstructor {
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break;
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case bw(PreDec): // [EORI/ORI/ANDI/SUBI/ADDI].bw #, -(An)
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op(int(is_byte_access ? Action::Decrement1 : Action::Decrement2) | MicroOp::DestinationMask);
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op(dec(ea_register) | MicroOp::DestinationMask);
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op( int(Action::AssembleWordDataFromPrefetch) | MicroOp::SourceMask,
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seq("np n nrd np", { a(ea_register) }, !is_byte_access));
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op(Action::PerformOperation, seq("nw", { a(ea_register) }, !is_byte_access));
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@ -1069,7 +1070,7 @@ struct ProcessorStorageConstructor {
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case bw(PostInc): // ADD/SUB.bw (An)+, Dn
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op(Action::None, seq("nr np", { a(ea_register) }, !is_byte_access));
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if(ea_mode == PostInc) {
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op(int(is_byte_access ? Action::Increment1 : Action::Increment2) | MicroOp::SourceMask);
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op(inc(ea_register) | MicroOp::SourceMask);
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}
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op(Action::PerformOperation);
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break;
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@ -1085,7 +1086,7 @@ struct ProcessorStorageConstructor {
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break;
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case bw(PreDec): // ADD/SUB.bw -(An), Dn
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op( int(is_byte_access ? Action::Decrement1 : Action::Decrement2) | MicroOp::SourceMask,
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op( dec(ea_register) | MicroOp::SourceMask,
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seq("n nr np", { a(ea_register) }, !is_byte_access));
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op(Action::PerformOperation);
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break;
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@ -1158,7 +1159,7 @@ struct ProcessorStorageConstructor {
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op(Action::None, seq("nrd np", { a(destination_register) }, !is_byte_access));
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op(Action::PerformOperation, seq("nw", { a(destination_register) }, !is_byte_access));
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if(ea_mode == PostInc) {
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op(int(is_byte_access ? Action::Increment1 : Action::Increment2) | MicroOp::DestinationMask);
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op(inc(destination_register) | MicroOp::DestinationMask);
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}
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break;
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@ -1172,7 +1173,7 @@ struct ProcessorStorageConstructor {
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break;
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case bw(PreDec): // ADD/SUB.bw Dn, -(An)
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op( int(is_byte_access ? Action::Decrement1 : Action::Decrement2) | MicroOp::DestinationMask,
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op( dec(destination_register) | MicroOp::DestinationMask,
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seq("n nrd np", { a(destination_register) }, !is_byte_access));
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op(Action::PerformOperation, seq("nw", { a(destination_register) }, !is_byte_access));
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break;
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@ -1346,7 +1347,7 @@ struct ProcessorStorageConstructor {
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op(Action::None, seq("nrd np", { a(ea_register) }, !is_byte_access));
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op(Action::PerformOperation, seq("nw", { a(ea_register) }, !is_byte_access));
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if(mode == PostInc) {
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op(int(is_byte_access ? Action::Increment1 : Action::Increment2) | MicroOp::DestinationMask);
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op(inc(ea_register) | MicroOp::DestinationMask);
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}
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break;
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@ -1362,7 +1363,7 @@ struct ProcessorStorageConstructor {
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break;
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case bw(PreDec): // [ADD/SUB]Q.bw #, -(An)
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op( int(is_byte_access ? Action::Decrement1 : Action::Decrement2) | MicroOp::DestinationMask,
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op( dec(ea_register) | MicroOp::DestinationMask,
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seq("n nrd np", { a(ea_register) }, !is_byte_access));
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op(Action::PerformOperation, seq("nw", { a(ea_register) }, !is_byte_access));
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break;
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@ -1445,12 +1446,12 @@ struct ProcessorStorageConstructor {
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op(Action::None, seq("nrd np", { a(ea_register) }, false));
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op(Action::PerformOperation, is_bclr ? seq("nw", { a(ea_register) }, false) : nullptr);
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if(mode == PostInc) {
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op(int(Action::Increment1) | MicroOp::DestinationMask);
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op(inc(ea_register) | MicroOp::DestinationMask);
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}
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break;
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case PreDec: // BTST.b Dn, -(An)
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op(int(Action::Decrement1) | MicroOp::DestinationMask, seq("n nrd np", { a(ea_register) }, false));
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op(dec(ea_register) | MicroOp::DestinationMask, seq("n nrd np", { a(ea_register) }, false));
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op(Action::PerformOperation, is_bclr ? seq("nw", { a(ea_register) }, false) : nullptr);
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break;
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@ -1501,13 +1502,13 @@ struct ProcessorStorageConstructor {
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op(int(Action::AssembleWordDataFromPrefetch) | MicroOp::SourceMask, seq("np nrd np", { a(ea_register) }, false));
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op(Action::PerformOperation, is_bclr ? seq("nw", { a(ea_register) }, false) : nullptr);
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if(mode == PostInc) {
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op(int(Action::Increment1) | MicroOp::DestinationMask);
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op(inc(ea_register) | MicroOp::DestinationMask);
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}
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break;
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case PreDec: // BTST.b #, -(An)
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op(int(Action::AssembleWordDataFromPrefetch) | MicroOp::SourceMask, seq("np"));
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op(int(Action::Decrement1) | MicroOp::DestinationMask, seq("n nrd np", { a(ea_register) }, false));
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op(dec(ea_register) | MicroOp::DestinationMask, seq("n nrd np", { a(ea_register) }, false));
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op(Action::PerformOperation, is_bclr ? seq("nw", { a(ea_register) }, false) : nullptr);
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break;
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@ -1547,7 +1548,16 @@ struct ProcessorStorageConstructor {
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storage_.instructions[instruction].source_address = &storage_.address_[ea_register];
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storage_.instructions[instruction].destination_address = &storage_.address_[destination_register];
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op( int(Action::Decrement1) | MicroOp::SourceMask | MicroOp::DestinationMask,
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const int source_dec = dec(ea_register);
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const int destination_dec = dec(destination_register);
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int first_action = source_dec | MicroOp::SourceMask | MicroOp::DestinationMask;
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if(source_dec != destination_dec) {
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first_action = source_dec | MicroOp::SourceMask;
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op(destination_dec | MicroOp::DestinationMask);
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}
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op( first_action,
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seq("n nr nr np nw", { a(ea_register), a(destination_register), a(destination_register) }, false));
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op(Action::PerformOperation);
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} else {
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@ -1628,7 +1638,7 @@ struct ProcessorStorageConstructor {
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op(Action::None, seq("nrd", { a(ea_register) }, !is_byte_access));
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op(Action::PerformOperation, seq("np nw", { a(ea_register) }, !is_byte_access));
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if(ea_mode == PostInc) {
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op(int(is_byte_access ? Action::Increment1 : Action::Increment2) | MicroOp::DestinationMask);
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op(inc(ea_register) | MicroOp::DestinationMask);
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}
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break;
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@ -1642,7 +1652,7 @@ struct ProcessorStorageConstructor {
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break;
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case bw(PreDec): // [CLR/NEG/NEGX/NOT].bw -(An)
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op( int(is_byte_access ? Action::Decrement1 : Action::Decrement2) | MicroOp::DestinationMask,
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op( dec(ea_register) | MicroOp::DestinationMask,
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seq("nrd", { a(ea_register) }, !is_byte_access));
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op(Action::PerformOperation, seq("np nw", { a(ea_register) }, !is_byte_access));
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break;
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@ -1715,7 +1725,7 @@ struct ProcessorStorageConstructor {
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case bw(PostInc): // CMP.bw (An)+, Dn
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op(Action::None, seq("nr np", { a(ea_register) }, !is_byte_access));
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if(mode == PostInc) {
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op(int(is_byte_access ? Action::Increment1 : Action::Increment2) | MicroOp::SourceMask);
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op(inc(ea_register) | MicroOp::SourceMask);
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}
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op(Action::PerformOperation);
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break;
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@ -1730,7 +1740,7 @@ struct ProcessorStorageConstructor {
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break;
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case bw(PreDec): // CMP.bw -(An), Dn
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op( int(is_byte_access ? Action::Decrement1 : Action::Decrement2) | MicroOp::SourceMask,
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op( dec(ea_register) | MicroOp::SourceMask,
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seq("n nr np", { a(ea_register) }, !is_byte_access));
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op(Action::PerformOperation);
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break;
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@ -1901,7 +1911,7 @@ struct ProcessorStorageConstructor {
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case bw(PostInc): // CMPI.bw #, (An)+
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op(int(Action::AssembleWordDataFromPrefetch) | MicroOp::SourceMask, seq("np nrd np", { a(destination_register) }, !is_byte_access));
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if(mode == PostInc) {
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op(int(is_byte_access ? Action::Increment1 : Action::Increment2) | MicroOp::DestinationMask);
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op(inc(destination_register) | MicroOp::DestinationMask);
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}
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op(Action::PerformOperation);
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break;
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@ -1918,7 +1928,7 @@ struct ProcessorStorageConstructor {
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case bw(PreDec): // CMPI.bw #, -(An)
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op(int(Action::AssembleWordDataFromPrefetch) | MicroOp::SourceMask, seq("np n"));
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op(int(is_byte_access ? Action::Decrement1 : Action::Decrement1) | MicroOp::DestinationMask, seq("nrd np", { a(destination_register) }, !is_byte_access));
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op(dec(destination_register) | MicroOp::DestinationMask, seq("nrd np", { a(destination_register) }, !is_byte_access));
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op(Action::PerformOperation);
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break;
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@ -1994,7 +2004,7 @@ struct ProcessorStorageConstructor {
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case Operation::CMPw: // CMPM.w, (An)+, (An)+
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op(Action::None, seq("nr nr np", {a(source_register), a(destination_register)}, !is_byte_operation));
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op(Action::PerformOperation);
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op(int(is_byte_operation ? Action::Increment1 : Action::Increment2) | MicroOp::SourceMask | MicroOp::DestinationMask);
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op(inc(destination_register) | MicroOp::SourceMask | MicroOp::DestinationMask);
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break;
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case Operation::CMPl:
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@ -2036,12 +2046,12 @@ struct ProcessorStorageConstructor {
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case PostInc:
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op(Action::PerformOperation, seq("nr np nw", { a(ea_register), a(ea_register) }, false));
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if(mode == PostInc) {
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op(int(Action::Increment1) | MicroOp::DestinationMask);
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op(inc(ea_register) | MicroOp::DestinationMask);
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}
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break;
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case PreDec:
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op(int(Action::Decrement1) | MicroOp::DestinationMask);
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op(dec(ea_register) | MicroOp::DestinationMask);
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op(Action::PerformOperation, seq("n nr np nw", { a(ea_register), a(ea_register) }, false));
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break;
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@ -2316,8 +2326,6 @@ struct ProcessorStorageConstructor {
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// These don't come from the usual place.
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is_byte_access = mapping.operation == Operation::MOVEb;
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is_long_word_access = mapping.operation == Operation::MOVEl;
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dec = decrement_action(is_long_word_access, is_byte_access);
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inc = increment_action(is_long_word_access, is_byte_access);
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const int combined_source_mode = combined_mode(ea_mode, ea_register, true, true);
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const int combined_destination_mode = combined_mode(destination_mode, destination_register, true, true);
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@ -2347,7 +2355,7 @@ struct ProcessorStorageConstructor {
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break;
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case l2(PreDec, Dn): // MOVE[A].l -(An), [An/Dn]
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op(dec | MicroOp::SourceMask, seq("n"));
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op(dec(ea_register) | MicroOp::SourceMask, seq("n"));
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case l2(Ind, Dn): // MOVE[A].l (An)[+], [An/Dn]
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op(int(Action::CopyToEffectiveAddress) | MicroOp::SourceMask, seq("nR+ nr np", { ea(0), ea(0) }));
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op(Action::PerformOperation);
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@ -2359,7 +2367,7 @@ struct ProcessorStorageConstructor {
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break;
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case bw2(PreDec, Dn): // MOVE[A].bw -(An), [An/Dn]
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op(dec | MicroOp::SourceMask, seq("n nr np", { a(ea_register) }, !is_byte_access));
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op(dec(ea_register) | MicroOp::SourceMask, seq("n nr np", { a(ea_register) }, !is_byte_access));
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op(Action::PerformOperation);
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break;
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@ -2413,7 +2421,7 @@ struct ProcessorStorageConstructor {
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break;
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case l2(PreDec, Ind): // MOVE.l -(An), (An)[+]
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op(dec | MicroOp::SourceMask, seq("n"));
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op(dec(ea_register) | MicroOp::SourceMask, seq("n"));
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case l2(Ind, Ind): // MOVE.l (An)[+], (An)[+]
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op( int(Action::CopyToEffectiveAddress) | MicroOp::DestinationMask | MicroOp::SourceMask,
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seq("nR+ nr", { ea(0), ea(0) }));
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@ -2426,7 +2434,7 @@ struct ProcessorStorageConstructor {
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break;
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case bw2(PreDec, Ind): // MOVE.bw -(An), (An)[+]
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op(dec | MicroOp::SourceMask, seq("n nr", { a(ea_register) }, !is_byte_access));
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op(dec(ea_register) | MicroOp::SourceMask, seq("n nr", { a(ea_register) }, !is_byte_access));
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op(Action::PerformOperation, seq("nw np", { a(destination_register) }, !is_byte_access));
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break;
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@ -2481,7 +2489,7 @@ struct ProcessorStorageConstructor {
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case bw2(Dn, PreDec): // MOVE.bw [An/Dn], -(An)
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op(Action::PerformOperation);
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op( dec| MicroOp::DestinationMask,
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op( dec(destination_register) | MicroOp::DestinationMask,
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seq("np nw", { a(destination_register) }, !is_byte_access));
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break;
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@ -2496,14 +2504,14 @@ struct ProcessorStorageConstructor {
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// e.g. MOVE.w -(A6), -(A6)
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case bw2(PreDec, PreDec): // MOVE.bw -(An), -(An)
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op(dec | MicroOp::SourceMask, seq("n"));
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op(dec(ea_register) | MicroOp::SourceMask, seq("n"));
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case bw2(Ind, PreDec): // MOVE.bw (An)[+], -(An)
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op(dec | MicroOp::DestinationMask, seq("nr", { a(ea_register) }, !is_byte_access));
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op(dec(destination_register) | MicroOp::DestinationMask, seq("nr", { a(ea_register) }, !is_byte_access));
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op(Action::PerformOperation, seq("np nw", { a(destination_register) }, !is_byte_access));
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break;
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case l2(PreDec, PreDec): // MOVE.l -(An), -(An)
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op(dec | MicroOp::SourceMask, seq("n"));
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op(dec(ea_register) | MicroOp::SourceMask, seq("n"));
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case l2(Ind, PreDec): // MOVE.l (An)[+], -(An)
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op(int(Action::CopyToEffectiveAddress) | MicroOp::SourceMask, seq("nR+ nr", { ea(0), ea(0) } ));
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op(Action::PerformOperation);
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@ -2522,7 +2530,7 @@ struct ProcessorStorageConstructor {
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op( address_action_for_mode(combined_source_mode) | MicroOp::SourceMask,
|
||||
seq(pseq("np nr", combined_source_mode), { ea(0) }, !is_byte_access ));
|
||||
op(Action::PerformOperation);
|
||||
op(dec | MicroOp::DestinationMask, seq("np nw", { a(destination_register) }, !is_byte_access));
|
||||
op(dec(destination_register) | MicroOp::DestinationMask, seq("np nw", { a(destination_register) }, !is_byte_access));
|
||||
break;
|
||||
|
||||
case l2(XXXl, PreDec): // MOVE.l (xxx).w, -(An)
|
||||
@ -2543,7 +2551,7 @@ struct ProcessorStorageConstructor {
|
||||
case bw2(Imm, PreDec): // MOVE.bw #, -(An)
|
||||
op(int(Action::AssembleWordDataFromPrefetch) | MicroOp::SourceMask, seq("np"));
|
||||
op(Action::PerformOperation);
|
||||
op(dec | MicroOp::DestinationMask, seq("np nw", { a(destination_register) }, !is_byte_access));
|
||||
op(dec(destination_register) | MicroOp::DestinationMask, seq("np nw", { a(destination_register) }, !is_byte_access));
|
||||
break;
|
||||
|
||||
case l2(Imm, PreDec): // MOVE.l #, -(An)
|
||||
@ -2587,13 +2595,13 @@ struct ProcessorStorageConstructor {
|
||||
break;
|
||||
|
||||
case bw2d(PreDec): // MOVE.bw -(An), (d16, An)/(d8, An, Xn)/(d16, PC)/(d8, PC, Xn)
|
||||
op(dec | MicroOp::SourceMask, seq("n nr", { a(ea_register) }, !is_byte_access));
|
||||
op(dec(ea_register) | MicroOp::SourceMask, seq("n nr", { a(ea_register) }, !is_byte_access));
|
||||
op(Action::PerformOperation);
|
||||
op(calc_action_for_mode(combined_destination_mode) | MicroOp::DestinationMask, seq("np nw np", { ea(1) }, !is_byte_access));
|
||||
break;
|
||||
|
||||
case l2d(PreDec): // MOVE.l -(An), (d16, An)/(d8, An, Xn)/(d16, PC)/(d8, PC, Xn)
|
||||
op(dec | MicroOp::SourceMask, seq("n"));
|
||||
op(dec(ea_register) | MicroOp::SourceMask, seq("n"));
|
||||
op(int(Action::CopyToEffectiveAddress) | MicroOp::SourceMask, seq("nR+ nr", { ea(0), ea(0) }));
|
||||
op(Action::PerformOperation);
|
||||
op(calc_action_for_mode(combined_destination_mode) | MicroOp::DestinationMask, seq("np nW+ nw np", { ea(1), ea(1) }));
|
||||
@ -2684,20 +2692,20 @@ struct ProcessorStorageConstructor {
|
||||
break;
|
||||
|
||||
case bw2(PreDec, XXXw): // MOVE.bw -(An), (xxx).W
|
||||
op( dec | MicroOp::SourceMask);
|
||||
op( dec(ea_register) | MicroOp::SourceMask);
|
||||
op( address_assemble_for_mode(combined_destination_mode) | MicroOp::DestinationMask,
|
||||
seq("n nr np", { a(ea_register) }, !is_byte_access));
|
||||
op(Action::PerformOperation, seq("nw np", { ea(1) }, !is_byte_access));
|
||||
break;
|
||||
|
||||
case bw2(PreDec, XXXl): // MOVE.bw -(An), (xxx).L
|
||||
op(dec | MicroOp::SourceMask, seq("n nr np", { a(ea_register) }, !is_byte_access));
|
||||
op(dec(ea_register) | MicroOp::SourceMask, seq("n nr np", { a(ea_register) }, !is_byte_access));
|
||||
op(address_assemble_for_mode(combined_destination_mode) | MicroOp::DestinationMask);
|
||||
op(Action::PerformOperation, seq("nw np np", { ea(1) }, !is_byte_access));
|
||||
break;
|
||||
|
||||
case l2(PreDec, XXXw): // MOVE.l -(An), (xxx).W
|
||||
op( dec | MicroOp::SourceMask);
|
||||
op( dec(ea_register) | MicroOp::SourceMask);
|
||||
op( int(Action::CopyToEffectiveAddress) | MicroOp::SourceMask,
|
||||
seq("n nR+ nr", { ea(0), ea(0) } ));
|
||||
op( address_assemble_for_mode(combined_destination_mode) | MicroOp::DestinationMask, seq("np"));
|
||||
@ -2706,7 +2714,7 @@ struct ProcessorStorageConstructor {
|
||||
break;
|
||||
|
||||
case l2(PreDec, XXXl): // MOVE.l -(An), (xxx).L
|
||||
op( dec | MicroOp::SourceMask);
|
||||
op( dec(ea_register) | MicroOp::SourceMask);
|
||||
op( int(Action::CopyToEffectiveAddress) | MicroOp::SourceMask,
|
||||
seq("n nR+ nr np", { ea(0), ea(0) } ));
|
||||
op( address_assemble_for_mode(combined_destination_mode) | MicroOp::DestinationMask, seq("np"));
|
||||
@ -2835,10 +2843,22 @@ struct ProcessorStorageConstructor {
|
||||
|
||||
// If any post-incrementing was involved, do the post increment(s).
|
||||
if(ea_mode == PostInc || destination_mode == PostInc) {
|
||||
op(
|
||||
inc |
|
||||
(ea_mode == PostInc ? MicroOp::SourceMask : 0) |
|
||||
(destination_mode == PostInc ? MicroOp::DestinationMask : 0));
|
||||
if(ea_mode == destination_mode) {
|
||||
const int ea_inc = inc(ea_mode);
|
||||
const int destination_inc = inc(destination_mode);
|
||||
if(ea_inc == destination_inc) {
|
||||
op(ea_inc | MicroOp::SourceMask | MicroOp::DestinationMask);
|
||||
} else {
|
||||
op(ea_inc | MicroOp::SourceMask);
|
||||
op(destination_inc | MicroOp::DestinationMask);
|
||||
}
|
||||
} else {
|
||||
if(ea_mode == PostInc) {
|
||||
op(inc(ea_mode) | MicroOp::SourceMask);
|
||||
} else {
|
||||
op(inc(destination_mode) | MicroOp::DestinationMask);
|
||||
}
|
||||
}
|
||||
}
|
||||
} break;
|
||||
|
||||
@ -2868,13 +2888,13 @@ struct ProcessorStorageConstructor {
|
||||
break;
|
||||
|
||||
case bw(PreDec): // TST.bw -(An)
|
||||
op(int(is_byte_access ? Action::Decrement1 : Action::Decrement2) | MicroOp::SourceMask, seq("n"));
|
||||
op(dec(ea_register) | MicroOp::SourceMask, seq("n"));
|
||||
case bw(Ind): // TST.bw (An)
|
||||
case bw(PostInc): // TST.bw (An)+
|
||||
op(Action::None, seq("nr", { a(ea_register) }, !is_byte_access));
|
||||
op(Action::PerformOperation, seq("np"));
|
||||
if(mode == PostInc) {
|
||||
op(int(is_byte_access ? Action::Increment1 : Action::Increment2) | MicroOp::SourceMask);
|
||||
op(inc(ea_register) | MicroOp::SourceMask);
|
||||
}
|
||||
break;
|
||||
|
||||
@ -2952,6 +2972,9 @@ struct ProcessorStorageConstructor {
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
#undef inc
|
||||
#undef dec
|
||||
}
|
||||
|
||||
#undef Dn
|
||||
|
||||
Loading…
Reference in New Issue
Block a user