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Decode [MUL/DIV][U/S].l.

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This commit is contained in:
Thomas Harte 2022-10-30 11:32:36 -04:00
parent 63ad2e8263
commit bbd2cd47ea
4 changed files with 131 additions and 112 deletions
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19
InstructionSets/M68k/Decoder.cpp
View File

@ -162,7 +162,7 @@ template <typename Predecoder<model>::OpT op> uint32_t Predecoder<model>::invali
//
// All modes: the complete set (other than Quick).
//
static constexpr auto AllModes = Dn | An | Ind | PostInc | PreDec | d16An | d8AnXn | XXXw | XXXl | d16PC | d8PCXn | Imm;
static constexpr auto AllModes = Dn | An | Ind | PostInc | PreDec | d16An | d8AnXn | XXXw | XXXl | Imm | d16PC | d8PCXn;
static constexpr auto AllModesNoAn = AllModes & ~An;
//
@ -606,6 +606,13 @@ template <typename Predecoder<model>::OpT op> uint32_t Predecoder<model>::invali
return ~OneOperandMask<
Dn
>::value;
case OpT(Operation::DIVSorDIVUl):
case OpT(Operation::MULSorMULUl):
return ~TwoOperandMask<
Ext,
AllModesNoAn
>::value;
}
return InvalidOperands;
@ -1108,7 +1115,8 @@ template <typename Predecoder<model>::OpT op, bool validate> Preinstruction Pred
// b0–b2 and b3–b5: source effective address.
// Plus an immediate word operand
//
case OpT(Operation::DIVSl):
case OpT(Operation::DIVSorDIVUl):
case OpT(Operation::MULSorMULUl):
return validated<op, validate>(
AddressingMode::ExtensionWord, 0,
combined_mode(ea_mode, ea_register), ea_register);
@ -1505,8 +1513,11 @@ Preinstruction Predecoder<model>::decode4(uint16_t instruction) {
// 4-108 (p212)
case 0xec0: Decode(Op::JMP);
// 4-94 (p198)
// case 0xc40: DecodeReq(model >= Model::M68020, Op::DIVSl);
// 4-94 (p198) [DIVS.l]; 4-98 (p202) [DIVU.l]
case 0xc40: DecodeReq(model >= Model::M68020, Op::DIVSorDIVUl);
// 4-137 (p241) [MULS.l]; 4-140 (p244) [MULU.l]
case 0xc00: DecodeReq(model >= Model::M68020, Op::MULSorMULUl);
// 4-121 (p225)
case 0x2c0: DecodeReq(model >= Model::M68010, Op::MOVEfromCCR);

3
InstructionSets/M68k/Instruction.cpp
View File

@ -238,8 +238,11 @@ const char *_to_string(Operation operation, bool is_quick) {
case Operation::MULUw: return "MULU";
case Operation::MULSw: return "MULS";
case Operation::MULSorMULUl: return "[MULS/MULU]{L}.l";
case Operation::DIVUw: return "DIVU";
case Operation::DIVSw: return "DIVS";
case Operation::DIVSorDIVUl: return "[DIVS/DIVU]{L}.l";
case Operation::RTE: return "RTE";
case Operation::RTR: return "RTR";

9
InstructionSets/M68k/Instruction.hpp
View File

@ -138,8 +138,13 @@ enum class Operation: uint8_t {
// to the full things, the following enums result.
CHKorCMP2b, CHKorCMP2w, CHKorCMP2l,
DIVSl, DIVUl,
MULSl, MULUl,
// DIVS.l, DIVSL.l, DIVU.l and DIVUL.l are all distinguishable
// only by the extension word.
DIVSorDIVUl,
// MULS.l, MULSL.l, MULU.l and MULUL.l are all distinguishable
// only by the extension word.
MULSorMULUl,
Bccl, BSRl,
LINKl, CHKl,

212
OSBindings/Mac/Clock SignalTests/68000 Decoding/68020ops.json
View File

@ -19455,14 +19455,14 @@
"4bfd": "None",
"4bfe": "None",
"4bff": "None",
"4c00": "None",
"4c01": "None",
"4c02": "None",
"4c03": "None",
"4c04": "None",
"4c05": "None",
"4c06": "None",
"4c07": "None",
"4c00": "[MULS/MULU]{L}.l #, D0",
"4c01": "[MULS/MULU]{L}.l #, D1",
"4c02": "[MULS/MULU]{L}.l #, D2",
"4c03": "[MULS/MULU]{L}.l #, D3",
"4c04": "[MULS/MULU]{L}.l #, D4",
"4c05": "[MULS/MULU]{L}.l #, D5",
"4c06": "[MULS/MULU]{L}.l #, D6",
"4c07": "[MULS/MULU]{L}.l #, D7",
"4c08": "None",
"4c09": "None",
"4c0a": "None",
@ -19471,62 +19471,62 @@
"4c0d": "None",
"4c0e": "None",
"4c0f": "None",
"4c10": "None",
"4c11": "None",
"4c12": "None",
"4c13": "None",
"4c14": "None",
"4c15": "None",
"4c16": "None",
"4c17": "None",
"4c18": "None",
"4c19": "None",
"4c1a": "None",
"4c1b": "None",
"4c1c": "None",
"4c1d": "None",
"4c1e": "None",
"4c1f": "None",
"4c20": "None",
"4c21": "None",
"4c22": "None",
"4c23": "None",
"4c24": "None",
"4c25": "None",
"4c26": "None",
"4c27": "None",
"4c28": "None",
"4c29": "None",
"4c2a": "None",
"4c2b": "None",
"4c2c": "None",
"4c2d": "None",
"4c2e": "None",
"4c2f": "None",
"4c30": "None",
"4c31": "None",
"4c32": "None",
"4c33": "None",
"4c34": "None",
"4c35": "None",
"4c36": "None",
"4c37": "None",
"4c38": "None",
"4c39": "None",
"4c3a": "None",
"4c3b": "None",
"4c3c": "None",
"4c10": "[MULS/MULU]{L}.l #, (A0)",
"4c11": "[MULS/MULU]{L}.l #, (A1)",
"4c12": "[MULS/MULU]{L}.l #, (A2)",
"4c13": "[MULS/MULU]{L}.l #, (A3)",
"4c14": "[MULS/MULU]{L}.l #, (A4)",
"4c15": "[MULS/MULU]{L}.l #, (A5)",
"4c16": "[MULS/MULU]{L}.l #, (A6)",
"4c17": "[MULS/MULU]{L}.l #, (A7)",
"4c18": "[MULS/MULU]{L}.l #, (A0)+",
"4c19": "[MULS/MULU]{L}.l #, (A1)+",
"4c1a": "[MULS/MULU]{L}.l #, (A2)+",
"4c1b": "[MULS/MULU]{L}.l #, (A3)+",
"4c1c": "[MULS/MULU]{L}.l #, (A4)+",
"4c1d": "[MULS/MULU]{L}.l #, (A5)+",
"4c1e": "[MULS/MULU]{L}.l #, (A6)+",
"4c1f": "[MULS/MULU]{L}.l #, (A7)+",
"4c20": "[MULS/MULU]{L}.l #, -(A0)",
"4c21": "[MULS/MULU]{L}.l #, -(A1)",
"4c22": "[MULS/MULU]{L}.l #, -(A2)",
"4c23": "[MULS/MULU]{L}.l #, -(A3)",
"4c24": "[MULS/MULU]{L}.l #, -(A4)",
"4c25": "[MULS/MULU]{L}.l #, -(A5)",
"4c26": "[MULS/MULU]{L}.l #, -(A6)",
"4c27": "[MULS/MULU]{L}.l #, -(A7)",
"4c28": "[MULS/MULU]{L}.l #, (d16, A0)",
"4c29": "[MULS/MULU]{L}.l #, (d16, A1)",
"4c2a": "[MULS/MULU]{L}.l #, (d16, A2)",
"4c2b": "[MULS/MULU]{L}.l #, (d16, A3)",
"4c2c": "[MULS/MULU]{L}.l #, (d16, A4)",
"4c2d": "[MULS/MULU]{L}.l #, (d16, A5)",
"4c2e": "[MULS/MULU]{L}.l #, (d16, A6)",
"4c2f": "[MULS/MULU]{L}.l #, (d16, A7)",
"4c30": "[MULS/MULU]{L}.l #, (d8, A0, Xn)",
"4c31": "[MULS/MULU]{L}.l #, (d8, A1, Xn)",
"4c32": "[MULS/MULU]{L}.l #, (d8, A2, Xn)",
"4c33": "[MULS/MULU]{L}.l #, (d8, A3, Xn)",
"4c34": "[MULS/MULU]{L}.l #, (d8, A4, Xn)",
"4c35": "[MULS/MULU]{L}.l #, (d8, A5, Xn)",
"4c36": "[MULS/MULU]{L}.l #, (d8, A6, Xn)",
"4c37": "[MULS/MULU]{L}.l #, (d8, A7, Xn)",
"4c38": "[MULS/MULU]{L}.l #, (xxx).w",
"4c39": "[MULS/MULU]{L}.l #, (xxx).l",
"4c3a": "[MULS/MULU]{L}.l #, (d16, PC)",
"4c3b": "[MULS/MULU]{L}.l #, (d8, PC, Xn)",
"4c3c": "[MULS/MULU]{L}.l #, #",
"4c3d": "None",
"4c3e": "None",
"4c3f": "None",
"4c40": "None",
"4c41": "None",
"4c42": "None",
"4c43": "None",
"4c44": "None",
"4c45": "None",
"4c46": "None",
"4c47": "None",
"4c40": "[DIVS/DIVU]{L}.l #, D0",
"4c41": "[DIVS/DIVU]{L}.l #, D1",
"4c42": "[DIVS/DIVU]{L}.l #, D2",
"4c43": "[DIVS/DIVU]{L}.l #, D3",
"4c44": "[DIVS/DIVU]{L}.l #, D4",
"4c45": "[DIVS/DIVU]{L}.l #, D5",
"4c46": "[DIVS/DIVU]{L}.l #, D6",
"4c47": "[DIVS/DIVU]{L}.l #, D7",
"4c48": "None",
"4c49": "None",
"4c4a": "None",
@ -19535,51 +19535,51 @@
"4c4d": "None",
"4c4e": "None",
"4c4f": "None",
"4c50": "None",
"4c51": "None",
"4c52": "None",
"4c53": "None",
"4c54": "None",
"4c55": "None",
"4c56": "None",
"4c57": "None",
"4c58": "None",
"4c59": "None",
"4c5a": "None",
"4c5b": "None",
"4c5c": "None",
"4c5d": "None",
"4c5e": "None",
"4c5f": "None",
"4c60": "None",
"4c61": "None",
"4c62": "None",
"4c63": "None",
"4c64": "None",
"4c65": "None",
"4c66": "None",
"4c67": "None",
"4c68": "None",
"4c69": "None",
"4c6a": "None",
"4c6b": "None",
"4c6c": "None",
"4c6d": "None",
"4c6e": "None",
"4c6f": "None",
"4c70": "None",
"4c71": "None",
"4c72": "None",
"4c73": "None",
"4c74": "None",
"4c75": "None",
"4c76": "None",
"4c77": "None",
"4c78": "None",
"4c79": "None",
"4c7a": "None",
"4c7b": "None",
"4c7c": "None",
"4c50": "[DIVS/DIVU]{L}.l #, (A0)",
"4c51": "[DIVS/DIVU]{L}.l #, (A1)",
"4c52": "[DIVS/DIVU]{L}.l #, (A2)",
"4c53": "[DIVS/DIVU]{L}.l #, (A3)",
"4c54": "[DIVS/DIVU]{L}.l #, (A4)",
"4c55": "[DIVS/DIVU]{L}.l #, (A5)",
"4c56": "[DIVS/DIVU]{L}.l #, (A6)",
"4c57": "[DIVS/DIVU]{L}.l #, (A7)",
"4c58": "[DIVS/DIVU]{L}.l #, (A0)+",
"4c59": "[DIVS/DIVU]{L}.l #, (A1)+",
"4c5a": "[DIVS/DIVU]{L}.l #, (A2)+",
"4c5b": "[DIVS/DIVU]{L}.l #, (A3)+",
"4c5c": "[DIVS/DIVU]{L}.l #, (A4)+",
"4c5d": "[DIVS/DIVU]{L}.l #, (A5)+",
"4c5e": "[DIVS/DIVU]{L}.l #, (A6)+",
"4c5f": "[DIVS/DIVU]{L}.l #, (A7)+",
"4c60": "[DIVS/DIVU]{L}.l #, -(A0)",
"4c61": "[DIVS/DIVU]{L}.l #, -(A1)",
"4c62": "[DIVS/DIVU]{L}.l #, -(A2)",
"4c63": "[DIVS/DIVU]{L}.l #, -(A3)",
"4c64": "[DIVS/DIVU]{L}.l #, -(A4)",
"4c65": "[DIVS/DIVU]{L}.l #, -(A5)",
"4c66": "[DIVS/DIVU]{L}.l #, -(A6)",
"4c67": "[DIVS/DIVU]{L}.l #, -(A7)",
"4c68": "[DIVS/DIVU]{L}.l #, (d16, A0)",
"4c69": "[DIVS/DIVU]{L}.l #, (d16, A1)",
"4c6a": "[DIVS/DIVU]{L}.l #, (d16, A2)",
"4c6b": "[DIVS/DIVU]{L}.l #, (d16, A3)",
"4c6c": "[DIVS/DIVU]{L}.l #, (d16, A4)",
"4c6d": "[DIVS/DIVU]{L}.l #, (d16, A5)",
"4c6e": "[DIVS/DIVU]{L}.l #, (d16, A6)",
"4c6f": "[DIVS/DIVU]{L}.l #, (d16, A7)",
"4c70": "[DIVS/DIVU]{L}.l #, (d8, A0, Xn)",
"4c71": "[DIVS/DIVU]{L}.l #, (d8, A1, Xn)",
"4c72": "[DIVS/DIVU]{L}.l #, (d8, A2, Xn)",
"4c73": "[DIVS/DIVU]{L}.l #, (d8, A3, Xn)",
"4c74": "[DIVS/DIVU]{L}.l #, (d8, A4, Xn)",
"4c75": "[DIVS/DIVU]{L}.l #, (d8, A5, Xn)",
"4c76": "[DIVS/DIVU]{L}.l #, (d8, A6, Xn)",
"4c77": "[DIVS/DIVU]{L}.l #, (d8, A7, Xn)",
"4c78": "[DIVS/DIVU]{L}.l #, (xxx).w",
"4c79": "[DIVS/DIVU]{L}.l #, (xxx).l",
"4c7a": "[DIVS/DIVU]{L}.l #, (d16, PC)",
"4c7b": "[DIVS/DIVU]{L}.l #, (d8, PC, Xn)",
"4c7c": "[DIVS/DIVU]{L}.l #, #",
"4c7d": "None",
"4c7e": "None",
"4c7f": "None",