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The test set doesn't seem to do word rotation.
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@ -313,13 +313,18 @@ struct Executor {
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} else {
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did_read = bus.template read<uint32_t>(address, value, registers_.mode(), trans);
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// "An address offset from a word boundary will cause the data to be rotated into the
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// register so that the addressed byte occuplies bits 0 to 7."
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switch(address & 3) {
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case 0: break;
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case 1: value = (value >> 8) | (value << 24); break;
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case 2: value = (value >> 16) | (value << 16); break;
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case 3: value = (value >> 24) | (value << 8); break;
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if constexpr (model != Model::ARMv2with32bitAddressing) {
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// "An address offset from a word boundary will cause the data to be rotated into the
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// register so that the addressed byte occuplies bits 0 to 7."
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//
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// (though the test set that inspired 'ARMv2with32bitAddressing' appears not to honour this;
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// test below assumes it went away by the version of ARM that set supports)
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switch(address & 3) {
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case 0: break;
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case 1: value = (value >> 8) | (value << 24); break;
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case 2: value = (value >> 16) | (value << 16); break;
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case 3: value = (value >> 24) | (value << 8); break;
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}
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}
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}
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@ -381,6 +381,7 @@ struct MemoryLedger {
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}
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uint32_t r15_mask = 0xffff'ffff;
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bool ignore_test = false;
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switch(instruction) {
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case 0x03110002:
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// tsteq r1, #2; per my reading this is LSL#0 so the original
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@ -395,7 +396,7 @@ struct MemoryLedger {
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// sheet specifically says for a shift-by-register that
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// "LSL by more than 32 has result zero, carry out zero" so I think
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// the test set is adrift on the following:
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if(test_count == 15) continue;
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ignore_test = test_count == 15 - 1;
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break;
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case 0xe090e00f:
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@ -422,6 +423,9 @@ struct MemoryLedger {
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} else {
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// Execute test and compare.
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++test_count;
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if(ignore_test) {
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continue;
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}
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if(instruction == 0xe4931000 && test_count == 3) {
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printf("");
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