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https://github.com/TomHarte/CLK.git
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Treat a phase mismatch as ending DMA.
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parent
2d8e260671
commit
beca7a01c2
@ -8,9 +8,9 @@
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#include "ncr5380.hpp"
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#include "ncr5380.hpp"
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//#ifndef NDEBUG
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#ifndef NDEBUG
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//#define NDEBUG
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#define NDEBUG
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//#endif
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#endif
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#define LOG_PREFIX "[5380] "
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#define LOG_PREFIX "[5380] "
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#include "../../Outputs/Log.hpp"
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#include "../../Outputs/Log.hpp"
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@ -75,6 +75,7 @@ void NCR5380::write(int address, uint8_t value, bool) {
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// bit 1: 1 = use DMA mode
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// bit 1: 1 = use DMA mode
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// bit 0: 1 = begin arbitration mode (device ID should be in register 0)
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// bit 0: 1 = begin arbitration mode (device ID should be in register 0)
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arbitration_in_progress_ = false;
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arbitration_in_progress_ = false;
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phase_mismatch_ = false;
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switch(mode_ & 0x3) {
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switch(mode_ & 0x3) {
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case 0x0:
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case 0x0:
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bus_output_ &= ~SCSI::Line::Busy;
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bus_output_ &= ~SCSI::Line::Busy;
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@ -249,6 +250,7 @@ void NCR5380::scsi_bus_did_change(SCSI::Bus *, SCSI::BusState new_state, double
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*/
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*/
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if((mode_ & 0x42) == 0x02 && new_state & SCSI::Line::Request && !phase_matches()) {
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if((mode_ & 0x42) == 0x02 && new_state & SCSI::Line::Request && !phase_matches()) {
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irq_ = true;
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irq_ = true;
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phase_mismatch_ = true;
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}
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}
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switch(state_) {
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switch(state_) {
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@ -311,7 +313,9 @@ void NCR5380::scsi_bus_did_change(SCSI::Bus *, SCSI::BusState new_state, double
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dma_request_ = false;
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dma_request_ = false;
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break;
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break;
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case SCSI::Line::Request:
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case SCSI::Line::Request:
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dma_request_ = true;
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// Don't issue a new DMA request if a phase mismatch has
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// been detected. This is a bit of reading between the lines.
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dma_request_ = !phase_mismatch_;
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break;
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break;
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case SCSI::Line::Request | SCSI::Line::Acknowledge:
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case SCSI::Line::Request | SCSI::Line::Acknowledge:
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dma_request_ = false;
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dma_request_ = false;
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@ -61,6 +61,7 @@ class NCR5380 final: public SCSI::Bus::Observer {
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bool end_of_dma_ = false;
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bool end_of_dma_ = false;
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bool irq_ = false;
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bool irq_ = false;
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bool phase_mismatch_ = false;
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enum class ExecutionState {
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enum class ExecutionState {
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None,
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None,
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