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mirror of https://github.com/TomHarte/CLK.git synced 2025-02-09 17:31:18 +00:00

Treat a phase mismatch as ending DMA.

This commit is contained in:
Thomas Harte 2022-09-15 16:34:06 -04:00
parent 2d8e260671
commit beca7a01c2
2 changed files with 9 additions and 4 deletions

View File

@ -8,9 +8,9 @@
#include "ncr5380.hpp" #include "ncr5380.hpp"
//#ifndef NDEBUG #ifndef NDEBUG
//#define NDEBUG #define NDEBUG
//#endif #endif
#define LOG_PREFIX "[5380] " #define LOG_PREFIX "[5380] "
#include "../../Outputs/Log.hpp" #include "../../Outputs/Log.hpp"
@ -75,6 +75,7 @@ void NCR5380::write(int address, uint8_t value, bool) {
// bit 1: 1 = use DMA mode // bit 1: 1 = use DMA mode
// bit 0: 1 = begin arbitration mode (device ID should be in register 0) // bit 0: 1 = begin arbitration mode (device ID should be in register 0)
arbitration_in_progress_ = false; arbitration_in_progress_ = false;
phase_mismatch_ = false;
switch(mode_ & 0x3) { switch(mode_ & 0x3) {
case 0x0: case 0x0:
bus_output_ &= ~SCSI::Line::Busy; bus_output_ &= ~SCSI::Line::Busy;
@ -249,6 +250,7 @@ void NCR5380::scsi_bus_did_change(SCSI::Bus *, SCSI::BusState new_state, double
*/ */
if((mode_ & 0x42) == 0x02 && new_state & SCSI::Line::Request && !phase_matches()) { if((mode_ & 0x42) == 0x02 && new_state & SCSI::Line::Request && !phase_matches()) {
irq_ = true; irq_ = true;
phase_mismatch_ = true;
} }
switch(state_) { switch(state_) {
@ -311,7 +313,9 @@ void NCR5380::scsi_bus_did_change(SCSI::Bus *, SCSI::BusState new_state, double
dma_request_ = false; dma_request_ = false;
break; break;
case SCSI::Line::Request: case SCSI::Line::Request:
dma_request_ = true; // Don't issue a new DMA request if a phase mismatch has
// been detected. This is a bit of reading between the lines.
dma_request_ = !phase_mismatch_;
break; break;
case SCSI::Line::Request | SCSI::Line::Acknowledge: case SCSI::Line::Request | SCSI::Line::Acknowledge:
dma_request_ = false; dma_request_ = false;

View File

@ -61,6 +61,7 @@ class NCR5380 final: public SCSI::Bus::Observer {
bool end_of_dma_ = false; bool end_of_dma_ = false;
bool irq_ = false; bool irq_ = false;
bool phase_mismatch_ = false;
enum class ExecutionState { enum class ExecutionState {
None, None,