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https://github.com/TomHarte/CLK.git
synced 2024-07-06 01:28:57 +00:00
Move ExecutionState into Implementation.hpp; use goto to avoid some double switches.
Re: the latter, yuck. Yuck yuck yuck. But it does mean I can stop going back and forth on how to structure conditionality on effective address generation segueing into fetches without doubling up on tests.
This commit is contained in:
Thomas Harte
parent
aa9e7eb7a2
commit
bef12f3d65
@ -15,6 +15,28 @@
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namespace CPU {
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namespace MC68000Mk2 {
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/// States for the state machine which are named by
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/// me for their purpose rather than automatically by file position.
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/// These are negative to avoid ambiguity with the other group.
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enum ExecutionState: int {
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Reset = std::numeric_limits<int>::min(),
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Decode,
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WaitForDTACK,
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FetchOperand,
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StoreOperand,
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// Various forms of perform; each of these will
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// perform the current instruction, then do the
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// indicated bus cycle.
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Perform_np,
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Perform_np_n,
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// MOVE has unique bus usage, so has a specialised state.
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MOVEWrite,
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};
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// MARK: - The state machine.
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template <class BusHandler, bool dtack_is_implicit, bool permit_overrun, bool signal_will_perform>
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@ -34,21 +56,23 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
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#define CheckOverrun() if constexpr (permit_overrun) ConsiderExit()
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// Sets `x` as the next state, and exits now if all remaining time has been extended and permit_overrun is true.
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#define MoveToState(x) state_ = (x); if (permit_overrun && time_remaining_ <= HalfCycles(0)) return
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// Jumps directly to the state otherwise.
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#define MoveToState(x) { state_ = ExecutionState::x; if (permit_overrun && time_remaining_ <= HalfCycles(0)) return; goto x; }
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// Sets the start position for state x.
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#define BeginState(x) case ExecutionState::x: x
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//
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// So basic structure is, in general:
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//
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// case Action:
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// BeginState(Action):
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// do_something();
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// Spend(20);
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// do_something_else();
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// Spend(10);
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// do_a_third_thing();
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// Spend(30);
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//
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// MoveToState(next_action);
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// break;
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// MoveToState(next_action);
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//
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// Additional notes:
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//
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@ -83,7 +107,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
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awaiting_dtack = x; \
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awaiting_dtack.length = HalfCycles(2); \
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post_dtack_state_ = __COUNTER__+1; \
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state_ = State::WaitForDTACK; \
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state_ = ExecutionState::WaitForDTACK; \
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break; \
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} \
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[[fallthrough]]; case __COUNTER__:
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@ -133,17 +157,18 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
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// Spin in place, one cycle at a time, until one of DTACK,
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// BERR or VPA is asserted.
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case State::WaitForDTACK:
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BeginState(WaitForDTACK):
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PerformBusOperation(awaiting_dtack);
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if(dtack_ || berr_ || vpa_) {
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state_ = post_dtack_state_;
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continue;
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}
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break;
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MoveToState(WaitForDTACK);
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// Perform the RESET exception, which seeds the stack pointer and program
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// counter, populates the prefetch queue, and then moves to instruction dispatch.
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case State::Reset:
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BeginState(Reset):
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IdleBus(7); // (n-)*5 nn
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// Establish general reset state.
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@ -168,12 +193,11 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
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IdleBus(1); // n
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Prefetch(); // np
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MoveToState(State::Decode);
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break;
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MoveToState(Decode);
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// Inspect the prefetch queue in order to decode the next instruction,
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// and segue into the fetching of operands.
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case State::Decode:
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BeginState(Decode):
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opcode_ = prefetch_.high.w;
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instruction_ = decoder_.decode(opcode_);
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instruction_address_ = program_counter_.l - 4;
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@ -201,7 +225,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
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// for CLR or MOVE SR, <ea>.
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//
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// TODO: add MOVE special case, somewhere.
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case State::FetchOperand:
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BeginState(FetchOperand):
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// Check that this operand is meant to be fetched.
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if(!(operand_flags_ & (1 << next_operand_))) {
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state_ = perform_state_;
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@ -214,8 +238,11 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
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case Mode::DataRegisterDirect:
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operand_[next_operand_] = registers_[instruction_.lreg(next_operand_)];
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++next_operand_;
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state_ = next_operand_ == 2 ? perform_state_ : State::FetchOperand;
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continue;
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if(next_operand_ == 2) {
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state_ = perform_state_;
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continue;
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}
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MoveToState(FetchOperand);
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default:
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assert(false);
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@ -225,11 +252,10 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
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// Store operand is a lot simpler: only one operand is ever stored, and its address
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// is already known. So this can either skip straight back to ::Decode if the target
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// is a register, otherwise a single write operation can occur.
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case State::StoreOperand:
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BeginState(StoreOperand):
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if(instruction_.mode(next_operand_) <= Mode::AddressRegisterDirect) {
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registers_[instruction_.lreg(next_operand_)] = operand_[next_operand_];
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state_ = State::Decode;
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continue;
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MoveToState(Decode);
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}
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// TODO: make a decision on how I'm going to deal with byte/word/longword.
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@ -241,27 +267,26 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
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//
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#define MoveToWritePhase() \
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next_operand_ = operand_flags_ >> 3; \
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MoveToState(operand_flags_ & 0x0c ? State::StoreOperand : State::Decode)
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if(operand_flags_ & 0x0c) MoveToState(StoreOperand) else MoveToState(Decode)
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case State::Perform_np:
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BeginState(Perform_np):
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InstructionSet::M68k::perform<InstructionSet::M68k::Model::M68000>(
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instruction_, operand_[0], operand_[1], status_, *static_cast<ProcessorBase *>(this));
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Prefetch(); // np
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MoveToWritePhase();
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MoveToWritePhase();
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break;
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case State::Perform_np_n:
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BeginState(Perform_np_n):
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InstructionSet::M68k::perform<InstructionSet::M68k::Model::M68000>(
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instruction_, operand_[0], operand_[1], status_, *static_cast<ProcessorBase *>(this));
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Prefetch(); // np
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IdleBus(1); // n
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MoveToWritePhase();
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break;
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MoveToWritePhase();
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#undef MoveToWritePhase
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// Various states TODO.
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default:
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printf("Unhandled state: %d\n", state_);
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assert(false);
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@ -296,11 +321,11 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
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using Mode = InstructionSet::M68k::AddressingMode;
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switch(instruction_.operation) {
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BIND(NBCD, instruction_.mode(0) == Mode::DataRegisterDirect ? State::Perform_np_n : State::Perform_np);
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BIND(NBCD, instruction_.mode(0) == Mode::DataRegisterDirect ? ExecutionState::Perform_np_n : ExecutionState::Perform_np);
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// MOVEs are a special case for having an operand they write but did not read. So they segue into a
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// specialised state for writing the result.
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BIND(MOVEw, State::MOVEWrite);
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BIND(MOVEw, ExecutionState::MOVEWrite);
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default:
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assert(false);
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@ -13,36 +13,13 @@
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#include "../../../InstructionSets/M68k/Perform.hpp"
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#include "../../../InstructionSets/M68k/Status.hpp"
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#include <limits>
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namespace CPU {
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namespace MC68000Mk2 {
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struct ProcessorBase: public InstructionSet::M68k::NullFlowController {
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/// States for the state machine which are named by
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/// me for their purpose rather than automatically by file position.
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/// These are negative to avoid ambiguity with the other group.
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enum State: int {
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Reset = -1,
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Decode = -2,
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WaitForDTACK = -3,
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FetchOperand = -4,
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StoreOperand = -5,
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// Various different effective address calculations.
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CalculateAnDn = -5,
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// Various forms of perform; each of these will
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// perform the current instruction, then do the
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// indicated bus cycle.
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Perform_np = -6,
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Perform_np_n = -7,
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// MOVE has unique bus usage, so has a specialised state.
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MOVEWrite = -8,
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};
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int state_ = State::Reset;
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int state_ = std::numeric_limits<int>::min();
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/// Counts time left on the clock before the current batch of processing
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/// is complete; may be less than zero.
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@ -137,14 +114,6 @@ struct ProcessorBase: public InstructionSet::M68k::NullFlowController {
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// some of these may persist across multiple calls to run_for.
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Microcycle idle{0};
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// Read a data word.
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Microcycle read_word_data_announce {
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Microcycle::Read | Microcycle::NewAddress | Microcycle::IsData
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};
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Microcycle read_word_data {
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Microcycle::Read | Microcycle::SameAddress | Microcycle::SelectWord | Microcycle::IsData
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};
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// Read a program word. All accesses via the program counter are word sized.
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Microcycle read_program_announce {
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Microcycle::Read | Microcycle::NewAddress | Microcycle::IsProgram
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@ -153,6 +122,28 @@ struct ProcessorBase: public InstructionSet::M68k::NullFlowController {
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Microcycle::Read | Microcycle::SameAddress | Microcycle::SelectWord | Microcycle::IsProgram
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};
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// Read a data word or byte.
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Microcycle read_word_data_announce {
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Microcycle::Read | Microcycle::NewAddress | Microcycle::IsData
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};
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Microcycle read_word_data {
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Microcycle::Read | Microcycle::SameAddress | Microcycle::SelectWord | Microcycle::IsData
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};
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Microcycle read_byte_data {
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Microcycle::Read | Microcycle::SameAddress | Microcycle::SelectByte | Microcycle::IsData
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};
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// Write a data word or byte.
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Microcycle write_word_data_announce {
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Microcycle::NewAddress | Microcycle::IsData
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};
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Microcycle write_word_data {
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Microcycle::SameAddress | Microcycle::SelectWord | Microcycle::IsData
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};
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Microcycle write_byte_data {
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Microcycle::SameAddress | Microcycle::SelectByte | Microcycle::IsData
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};
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// Holding spot when awaiting DTACK/etc.
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Microcycle awaiting_dtack;
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};
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