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https://github.com/TomHarte/CLK.git
synced 2026-04-19 19:16:34 +00:00
Fix base RAM mapping.
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@@ -53,6 +53,7 @@ const std::vector<uint8_t> &MemorySlot::source() const {
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return source_;
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}
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template <MSX::MemorySlot::AccessType type>
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void MemorySlot::map(int subslot, std::size_t source_address, uint16_t destination_address, std::size_t length) {
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assert(!(destination_address & 8191));
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assert(!(length & 8191));
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@@ -60,7 +61,13 @@ void MemorySlot::map(int subslot, std::size_t source_address, uint16_t destinati
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for(std::size_t c = 0; c < (length >> 13); ++c) {
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source_address %= source_.size();
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read_pointers_[subslot][(destination_address >> 13) + c] = &source_[source_address];
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const int bank = int((destination_address >> 13) + c);
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read_pointers_[subslot][bank] = &source_[source_address];
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if constexpr (type == AccessType::ReadWrite) {
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write_pointers_[subslot][bank] = read_pointers_[subslot][bank];
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}
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source_address += 8192;
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}
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@@ -79,3 +86,6 @@ void MemorySlot::unmap(int subslot, uint16_t destination_address, std::size_t le
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// TODO: need to indicate that mapping changed.
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}
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template void MemorySlot::map<MSX::MemorySlot::AccessType::Read>(int subslot, std::size_t source_address, uint16_t destination_address, std::size_t length);
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template void MemorySlot::map<MSX::MemorySlot::AccessType::ReadWrite>(int subslot, std::size_t source_address, uint16_t destination_address, std::size_t length);
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