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mirror of https://github.com/TomHarte/CLK.git synced 2026-04-19 19:16:34 +00:00

Fix base RAM mapping.

This commit is contained in:
Thomas Harte
2023-01-13 09:31:56 -05:00
parent 23ff3fc366
commit befc81743a
3 changed files with 18 additions and 3 deletions
+11 -1
View File
@@ -53,6 +53,7 @@ const std::vector<uint8_t> &MemorySlot::source() const {
return source_;
}
template <MSX::MemorySlot::AccessType type>
void MemorySlot::map(int subslot, std::size_t source_address, uint16_t destination_address, std::size_t length) {
assert(!(destination_address & 8191));
assert(!(length & 8191));
@@ -60,7 +61,13 @@ void MemorySlot::map(int subslot, std::size_t source_address, uint16_t destinati
for(std::size_t c = 0; c < (length >> 13); ++c) {
source_address %= source_.size();
read_pointers_[subslot][(destination_address >> 13) + c] = &source_[source_address];
const int bank = int((destination_address >> 13) + c);
read_pointers_[subslot][bank] = &source_[source_address];
if constexpr (type == AccessType::ReadWrite) {
write_pointers_[subslot][bank] = read_pointers_[subslot][bank];
}
source_address += 8192;
}
@@ -79,3 +86,6 @@ void MemorySlot::unmap(int subslot, uint16_t destination_address, std::size_t le
// TODO: need to indicate that mapping changed.
}
template void MemorySlot::map<MSX::MemorySlot::AccessType::Read>(int subslot, std::size_t source_address, uint16_t destination_address, std::size_t length);
template void MemorySlot::map<MSX::MemorySlot::AccessType::ReadWrite>(int subslot, std::size_t source_address, uint16_t destination_address, std::size_t length);