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mirror of https://github.com/TomHarte/CLK.git synced 2026-04-26 03:29:40 +00:00

Standardises on read and write for bus accesses.

Logic being: name these things for the bus action they model, not the effect they have.
This commit is contained in:
Thomas Harte
2020-01-05 13:40:02 -05:00
parent b3f806201b
commit c1bae49a92
31 changed files with 100 additions and 100 deletions
@@ -30,7 +30,7 @@ template <typename T> void MOS6522<T>::access(int address) {
}
}
template <typename T> void MOS6522<T>::set_register(int address, uint8_t value) {
template <typename T> void MOS6522<T>::write(int address, uint8_t value) {
address &= 0xf;
access(address);
switch(address) {
@@ -155,7 +155,7 @@ template <typename T> void MOS6522<T>::set_register(int address, uint8_t value)
}
}
template <typename T> uint8_t MOS6522<T>::get_register(int address) {
template <typename T> uint8_t MOS6522<T>::read(int address) {
address &= 0xf;
access(address);
switch(address) {