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Standardises on read and write for bus accesses.

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Logic being: name these things for the bus action they model, not the effect they have.
This commit is contained in:
Thomas Harte
2020-01-05 13:40:02 -05:00
parent b3f806201b
commit c1bae49a92
31 changed files with 100 additions and 100 deletions
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Components/9918/9918.cpp
+2 -2
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@@ -492,7 +492,7 @@ void Base::output_border(int cycles, uint32_t cram_dot) {
}
}
void TMS9918::set_register(int address, uint8_t value) {
void TMS9918::write(int address, uint8_t value) {
// Writes to address 0 are writes to the video RAM. Store
// the value and return.
if(!(address & 1)) {
@@ -670,7 +670,7 @@ void TMS9918::latch_horizontal_counter() {
latched_column_ = write_pointer_.column;
}
uint8_t TMS9918::get_register(int address) {
uint8_t TMS9918::read(int address) {
write_phase_ = false;
// Reads from address 0 read video RAM, via the read-ahead buffer.