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mirror of https://github.com/TomHarte/CLK.git synced 2025-08-15 14:27:29 +00:00

Corrects byte writes in both test machines.

This commit is contained in:
Thomas Harte
2019-04-17 16:39:10 -04:00
parent 29f8dcfb40
commit c265ea9847
2 changed files with 3 additions and 3 deletions

View File

@@ -82,7 +82,7 @@ class EmuTOS: public CPU::MC68000::BusHandler {
break; break;
case Microcycle::SelectByte: case Microcycle::SelectByte:
assert(!(is_rom && !is_peripheral)); assert(!(is_rom && !is_peripheral));
base[word_address] = (cycle.value->full & cycle.byte_mask()) | (base[word_address] & (0xffff ^ cycle.byte_mask())); base[word_address] = (cycle.value->halves.low << cycle.byte_shift()) | (base[word_address] & (0xffff ^ cycle.byte_mask()));
break; break;
} }
} }

View File

@@ -84,8 +84,8 @@ class QL: public CPU::MC68000::BusHandler {
break; break;
case Microcycle::SelectByte: case Microcycle::SelectByte:
assert(!(is_rom && !is_peripheral)); assert(!(is_rom && !is_peripheral));
if(!(cycle.operation & Microcycle::IsProgram)) printf("[byte w %02x -> %08x] ", (cycle.value->full >> cycle.byte_shift()) & 0xff, *cycle.address); if(!(cycle.operation & Microcycle::IsProgram)) printf("[byte w %02x -> %08x] ", cycle.value->halves.low, *cycle.address);
if(!is_peripheral) base[word_address] = (cycle.value->full & cycle.byte_mask()) | (base[word_address] & (0xffff ^ cycle.byte_mask())); if(!is_peripheral) base[word_address] = (cycle.value->halves.low << cycle.byte_shift()) | (base[word_address] & (0xffff ^ cycle.byte_mask()));
break; break;
} }
} }