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mirror of https://github.com/TomHarte/CLK.git synced 2024-07-04 18:29:40 +00:00

Adds a received_data_ register, that presently can never fill.

This commit is contained in:
Thomas Harte 2019-10-13 23:04:57 -04:00
parent 530e831064
commit c352d8ae8c
2 changed files with 9 additions and 6 deletions

View File

@ -29,7 +29,8 @@ uint8_t ACIA::read(int address) {
} else {
LOG("Read status");
return
((next_transmission_ == NoTransmission) ? 0x02 : 0x00) |
((received_data_ == NoValue) ? 0x00 : 0x01) |
((next_transmission_ == NoValue) ? 0x02 : 0x00) |
(data_carrier_detect.read() ? 0x04 : 0x00) |
(clear_to_send.read() ? 0x08 : 0x00) |
(interrupt_request_ ? 0x80 : 0x00)
@ -98,7 +99,7 @@ void ACIA::run_for(HalfCycles length) {
if(write_data_time_remaining) {
if(transmit_advance >= write_data_time_remaining) {
if(next_transmission_ != NoTransmission) {
if(next_transmission_ != NoValue) {
transmit.flush_writing();
consider_transmission();
transmit.advance_writer(transmit_advance - write_data_time_remaining);
@ -116,7 +117,7 @@ void ACIA::run_for(HalfCycles length) {
}
void ACIA::consider_transmission() {
if(next_transmission_ != NoTransmission && !transmit.write_data_time_remaining()) {
if(next_transmission_ != NoValue && !transmit.write_data_time_remaining()) {
// Establish start bit and [7 or 8] data bits.
if(data_bits_ == 7) next_transmission_ &= 0x7f;
int transmission = next_transmission_ << 1;
@ -145,7 +146,7 @@ void ACIA::consider_transmission() {
transmit.write(divider_ * 2, total_bits, transmission);
// Mark the transmit register as empty again.
next_transmission_ = NoTransmission;
next_transmission_ = NoValue;
}
}

View File

@ -69,8 +69,10 @@ class ACIA: public ClockingHint::Source {
} parity_ = Parity::None;
int data_bits_ = 7, stop_bits_ = 2;
static const int NoTransmission = 0x100;
int next_transmission_ = NoTransmission;
static const int NoValue = 0x100;
int next_transmission_ = NoValue;
int received_data_ = NoValue;
void consider_transmission();
bool receive_interrupt_enabled_ = false;