From c97245e62663dd916bbba0942ca3c548bb8772ae Mon Sep 17 00:00:00 2001
From: Thomas Harte <thomas.harte@gmail.com>
Date: Fri, 27 May 2022 10:32:28 -0400
Subject: [PATCH 1/2] Fix CalcEA timing; make MOVEfromSR a read-modify-write.

---
 .../InstructionOperandFlags.hpp               |  5 ++--
 .../Implementation/68000Mk2Implementation.hpp | 28 +++++++++----------
 2 files changed, 17 insertions(+), 16 deletions(-)

diff --git a/InstructionSets/M68k/Implementation/InstructionOperandFlags.hpp b/InstructionSets/M68k/Implementation/InstructionOperandFlags.hpp
index 6c83cd310..ca29cc574 100644
--- a/InstructionSets/M68k/Implementation/InstructionOperandFlags.hpp
+++ b/InstructionSets/M68k/Implementation/InstructionOperandFlags.hpp
@@ -45,7 +45,7 @@ template <Model model, Operation t_operation> constexpr uint8_t operand_flags(Op
 		//
 		//	Single-operand write.
 		//
-		case Operation::MOVEfromSR:	case Operation::MOVEfromUSP:
+		case Operation::MOVEfromUSP:
 			return StoreOp1;
 
 		//
@@ -66,8 +66,9 @@ template <Model model, Operation t_operation> constexpr uint8_t operand_flags(Op
 			return FetchOp1 | StoreOp1;
 
 		//
-		//	CLR, which is model-dependent.
+		//	CLR and MOVE SR, which are model-dependent.
 		//
+		case Operation::MOVEfromSR:
 		case Operation::CLRb:	case Operation::CLRw:	case Operation::CLRl:
 			if constexpr (model == Model::M68000) {
 				return FetchOp1 | StoreOp1;
diff --git a/Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp b/Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp
index 4f319391c..3ae467571 100644
--- a/Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp
+++ b/Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp
@@ -86,16 +86,16 @@ enum ExecutionState: int {
 	FetchAbsoluteLong_l,
 	FetchImmediateData_l,
 
-	CalcEffectiveAddress,
-	CalcAddressRegisterIndirect,
-	CalcAddressRegisterIndirectWithPostincrement,
-	CalcAddressRegisterIndirectWithPredecrement,
-	CalcAddressRegisterIndirectWithDisplacement,
-	CalcAddressRegisterIndirectWithIndex8bitDisplacement,
-	CalcProgramCounterIndirectWithDisplacement,
-	CalcProgramCounterIndirectWithIndex8bitDisplacement,
-	CalcAbsoluteShort,
-	CalcAbsoluteLong,
+	CalcEffectiveAddress,											// -
+	CalcAddressRegisterIndirect,									// -
+	CalcAddressRegisterIndirectWithPostincrement,					// -
+	CalcAddressRegisterIndirectWithPredecrement,					// -
+	CalcAddressRegisterIndirectWithDisplacement,					// np
+	CalcAddressRegisterIndirectWithIndex8bitDisplacement,			// n np n
+	CalcProgramCounterIndirectWithDisplacement,						// np
+	CalcProgramCounterIndirectWithIndex8bitDisplacement,			// n np n
+	CalcAbsoluteShort,												// np
+	CalcAbsoluteLong,												// np np
 
 	// Various forms of perform; each of these will
 	// perform the current instruction, then do the
@@ -941,14 +941,12 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
 
 				Duplicate(MOVEtoCCR, MOVEtoSR);
 				StdCASE(MOVEtoSR, 	perform_state_ = MOVEtoCCRSR);
-
 				StdCASE(MOVEfromSR, {
 					if(instruction_.mode(0) == Mode::DataRegisterDirect) {
-						post_ea_state_ = Perform_np_n;
+						perform_state_ = Perform_np_n;
 					} else {
-						post_ea_state_ = Perform_np;
+						perform_state_ = Perform_np;
 					}
-					MoveToStateSpecific(CalcEffectiveAddress);
 				});
 
 				SpecialCASE(RTR);
@@ -1322,6 +1320,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
 
 		BeginState(CalcAddressRegisterIndirectWithIndex8bitDisplacement):
 			effective_address_[next_operand_].l = d8Xn(registers_[8 + instruction_.reg(next_operand_)].l);
+			IdleBus(1);								// n
 			Prefetch();								// np
 			IdleBus(1);								// n
 		MoveToStateDynamic(post_ea_state_);
@@ -1357,6 +1356,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
 
 		BeginState(CalcProgramCounterIndirectWithIndex8bitDisplacement):
 			effective_address_[next_operand_].l = d8Xn(program_counter_.l - 2);
+			IdleBus(1);								// n
 			Prefetch();								// np
 			IdleBus(1);								// n
 		MoveToStateDynamic(post_ea_state_);

From 67b340fa5e9ab0d2fbc372777ddec86d1a44ec20 Mon Sep 17 00:00:00 2001
From: Thomas Harte <thomas.harte@gmail.com>
Date: Thu, 26 May 2022 20:20:28 -0400
Subject: [PATCH 2/2] Fix interrupt request address.

---
 Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp b/Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp
index 3ae467571..921b182b9 100644
--- a/Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp
+++ b/Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp
@@ -531,7 +531,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
 			Access(captured_status_);			// ns
 
 			// Do the interrupt cycle, to obtain a vector.
-			temporary_address_.l = 0xffff'fff8 | uint32_t(captured_interrupt_level_);
+			temporary_address_.l = 0xffff'fff1 | uint32_t(captured_interrupt_level_ << 1);
 			SetupDataAccess(0, Microcycle::InterruptAcknowledge);
 			SetDataAddress(temporary_address_.l);
 			Access(temporary_value_.low);		// ni
@@ -541,6 +541,8 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
 				temporary_value_.w = uint16_t(InstructionSet::M68k::Exception::InterruptAutovectorBase - 1 + captured_interrupt_level_);
 			}
 
+			// TODO: if bus error is set, treat interrupt as spurious.
+
 			IdleBus(3);			// n- n
 
 			// Do the rest of the stack work.