1
0
mirror of https://github.com/TomHarte/CLK.git synced 2024-07-07 23:29:06 +00:00

This'll do as a write interface, won't it?

This commit is contained in:
Thomas Harte 2016-12-07 22:19:20 -05:00
parent 46ebae7e4b
commit c4041b06a8

View File

@ -59,6 +59,24 @@ class Controller: public DigitalPhaseLockedLoop::Delegate, public TimedEventLoop
*/ */
bool get_motor_on(); bool get_motor_on();
/*!
Begins write mode, initiating a PCM sampled region of data. During write mode, no events will
be reported. Bits should be written via @c write_bit. They will be written with the length set
via @c set_expected_bit_length.
*/
void begin_writing();
/*!
Writes the bit @c value as the next in the PCM stream initiated by @c begin_writing.
*/
void write_bit(bool value);
/*!
Ends write mode, switching back to read mode. The drive will return to posting events based
on the recorded track.
*/
void end_writing();
/*! /*!
Should be implemented by subclasses; communicates each bit that the PLL recognises, also specifying Should be implemented by subclasses; communicates each bit that the PLL recognises, also specifying
the amount of time since the index hole was last seen. the amount of time since the index hole was last seen.