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https://github.com/TomHarte/CLK.git
synced 2025-02-23 18:29:16 +00:00
Mild clean ups, and a tweak to permitted top and bottom phase.
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@ -15,7 +15,7 @@ const int PLLClockRate = 1920000;
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}
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}
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Parser::Parser() :
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Parser::Parser() :
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::Storage::Tape::PLLParser<SymbolType>(PLLClockRate, PLLClockRate / 4800, 100),
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::Storage::Tape::PLLParser<SymbolType>(PLLClockRate, PLLClockRate / 4800, PLLClockRate / 24000),
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crc_(0x1021, 0x0000) {}
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crc_(0x1021, 0x0000) {}
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int Parser::get_next_bit(const std::shared_ptr<Storage::Tape::Tape> &tape) {
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int Parser::get_next_bit(const std::shared_ptr<Storage::Tape::Tape> &tape) {
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@ -204,8 +204,10 @@ template <typename SymbolType> class PLLParser:
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private:
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private:
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Storage::DigitalPhaseLockedLoop pll_;
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Storage::DigitalPhaseLockedLoop pll_;
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int clock_rate_;
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int clock_rate_;
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int input_pattern_;
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int input_pattern_;
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int input_bit_counter_;
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int input_bit_counter_;
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bool was_high_;
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bool was_high_;
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};
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};
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