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Mental delusion lifted: JSR doesn't look enough like BSR.

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This commit is contained in:
Thomas Harte 2019-04-17 10:02:14 -04:00
parent b64da2710a
commit cadc0bd509
3 changed files with 15 additions and 11 deletions
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11
Processors/68000/Implementation/68000Implementation.hpp
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@ -1085,10 +1085,13 @@ template <class T, bool dtack_is_implicit> void Processor<T, dtack_is_implicit>:
}
} break;
case int(MicroOp::Action::PrepareJSRBSR):
// If the lowest byte of the instruction is non-zero then there's no 16-bit offset after it, so the
// return address should be two less. This holds for both a BSR and a JSR as a JSR always has bit
// 7 set.
case int(MicroOp::Action::PrepareJSR):
destination_bus_data_[0].full = program_counter_.full;
address_[7].full -= 4;
effective_address_[1].full = address_[7].full;
break;
case int(MicroOp::Action::PrepareBSR):
destination_bus_data_[0].full = (decoded_instruction_ & 0xff) ? program_counter_.full - 2 : program_counter_.full;
address_[7].full -= 4;
effective_address_[1].full = address_[7].full;

12
Processors/68000/Implementation/68000Storage.cpp
View File

@ -1125,7 +1125,7 @@ struct ProcessorStorageConstructor {
// This is BSR, which is unconditional and means pushing a return address to the stack first.
// Push the return address to the stack.
op(Action::PrepareJSRBSR, seq("n nW+ nw", { ea(1), ea(1) }));
op(Action::PrepareBSR, seq("n nW+ nw", { ea(1), ea(1) }));
}
// This is Bcc.
@ -1808,33 +1808,33 @@ struct ProcessorStorageConstructor {
default: continue;
case Ind: // JSR (An)
storage_.instructions[instruction].source = &storage_.address_[ea_register];
op(Action::PrepareJSRBSR);
op(Action::PrepareJSR);
op(Action::PerformOperation, seq("np nW+ nw np", { ea(1), ea(1) }));
break;
case d16PC: // JSR (d16, PC)
case d16An: // JSR (d16, An)
op(Action::PrepareJSRBSR);
op(Action::PrepareJSR);
op(calc_action_for_mode(mode) | MicroOp::SourceMask);
op(Action::PerformOperation, seq("n np nW+ nw np", { ea(1), ea(1) }));
break;
case d8PCXn: // JSR (d8, PC, Xn)
case d8AnXn: // JSR (d8, An, Xn)
op(Action::PrepareJSRBSR);
op(Action::PrepareJSR);
op(calc_action_for_mode(mode) | MicroOp::SourceMask);
op(Action::PerformOperation, seq("n nn np nW+ nw np", { ea(1), ea(1) }));
break;
case XXXl: // JSR (xxx).L
op(Action::None, seq("np"));
op(Action::PrepareJSRBSR);
op(Action::PrepareJSR);
op(address_assemble_for_mode(mode) | MicroOp::SourceMask);
op(Action::PerformOperation, seq("n np nW+ nw np", { ea(1), ea(1) }));
break;
case XXXw: // JSR (xxx).W
op(Action::PrepareJSRBSR);
op(Action::PrepareJSR);
op(address_assemble_for_mode(mode) | MicroOp::SourceMask);
op(Action::PerformOperation, seq("n np nW+ nw np", { ea(1), ea(1) }));
break;

3
Processors/68000/Implementation/68000Storage.hpp
View File

@ -233,7 +233,8 @@ class ProcessorStorage {
// (i) inspects the prefetch queue to determine the length of this instruction and copies the next PC to destination_bus_data_;
// (ii) copies the stack pointer minus 4 to effective_address_[1];
// (iii) decrements the stack pointer by four.
PrepareJSRBSR,
PrepareJSR,
PrepareBSR,
// (i) copies the stack pointer to effective_address_[0];
// (ii) increments the stack pointer by four.