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Start the process of decoding 68020 operations.
This commit is contained in:
Thomas Harte
parent
9be9e1ab0c
commit
cb0e259339
@ -316,6 +316,7 @@ template <uint8_t op> uint32_t Predecoder<model>::invalid_operands() {
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case OpT(Operation::Bccb):
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case OpT(Operation::BSRb):
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case OpT(Operation::TRAP):
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case OpT(Operation::BKPT):
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return ~OneOperandMask<
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Quick
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>::value;
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@ -335,6 +336,20 @@ template <uint8_t op> uint32_t Predecoder<model>::invalid_operands() {
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AllModesNoAn
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>::value;
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case OpT(Operation::BFCHG): case OpT(Operation::BFCLR): case OpT(Operation::BFSET):
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case OpT(Operation::BFINS):
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return ~TwoOperandMask<
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Imm,
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Dn | Ind | d16An | d8AnXn | XXXw | XXXl
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>::value;
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case OpT(Operation::BFTST): case OpT(Operation::BFFFO): case OpT(Operation::BFEXTU):
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case OpT(Operation::BFEXTS):
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return ~TwoOperandMask<
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Imm,
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Dn | Ind | d16An | d8AnXn | XXXw | XXXl | d16PC | d8PCXn
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>::value;
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case CMPIb: case CMPIl: case CMPIw:
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if constexpr (model == Model::M68000) {
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return ~TwoOperandMask<
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@ -421,6 +436,16 @@ template <uint8_t op> uint32_t Predecoder<model>::invalid_operands() {
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Dn
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>::value;
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case OpT(Operation::RTD):
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return ~OneOperandMask<
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Imm
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>::value;
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case OpT(Operation::CALLM):
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return ~OneOperandMask<
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ControlAddressingModes
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>::value;
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case OpT(Operation::JMP):
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case OpT(Operation::JSR):
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case OpT(Operation::PEA):
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@ -802,10 +827,11 @@ template <uint8_t op, bool validate> Preinstruction Predecoder<model>::decode(ui
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combined_mode(ea_mode, ea_register), ea_register);
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//
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// MARK: TRAP, BCCb, BSRb
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// MARK: TRAP, BCCb, BSRb, BKPT
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//
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// No further operands decoded, but note that one is somewhere in the opcode.
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// No further operands decoded, but one is somewhere in the opcode.
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//
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case OpT(Operation::BKPT):
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case OpT(Operation::TRAP):
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case OpT(Operation::BSRb):
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return validated<op, validate>(AddressingMode::Quick);
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@ -858,6 +884,7 @@ template <uint8_t op, bool validate> Preinstruction Predecoder<model>::decode(ui
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// b0–b2: a register to shift (the source here, for consistency with the memory operations);
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// b8: 0 => b9–b11 are a direct count of bits to shift; 1 => b9–b11 identify a register containing the shift count;
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// b9–b11: either a quick value or a register.
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//
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case OpT(Operation::ASRb): case OpT(Operation::ASRw): case OpT(Operation::ASRl):
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case OpT(Operation::LSRb): case OpT(Operation::LSRw): case OpT(Operation::LSRl):
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case OpT(Operation::ROXRb): case OpT(Operation::ROXRw): case OpT(Operation::ROXRl):
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@ -886,6 +913,36 @@ template <uint8_t op, bool validate> Preinstruction Predecoder<model>::decode(ui
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AddressingMode::AddressRegisterIndirectWithPostincrement, ea_register,
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AddressingMode::AddressRegisterIndirectWithPostincrement, data_register);
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//
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// MARK: BFCHG, BFTST, BFFFO, BFEXTU, BFEXTS, BFCLR, BFSET, BFINS
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//
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// b0–b2 and b3–b5: an effective address.
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// There is also an immedate operand describing an offset and width.
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//
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case OpT(Operation::BFCHG): case OpT(Operation::BFTST): case OpT(Operation::BFFFO):
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case OpT(Operation::BFEXTU): case OpT(Operation::BFEXTS): case OpT(Operation::BFCLR):
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case OpT(Operation::BFSET): case OpT(Operation::BFINS):
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return validated<op, validate>(
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AddressingMode::ImmediateData, 0,
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combined_mode(ea_mode, ea_register), ea_register);
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//
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// MARK: CALLM
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//
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// b0–b2 and b3–b5: an effective address.
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// There is also an immedate operand providing argument count.
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//
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case OpT(Operation::CALLM):
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return validated<op, validate>(
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AddressingMode::ImmediateData, 0,
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combined_mode(ea_mode, ea_register), ea_register);
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//
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// MARK: RTD
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//
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case OpT(Operation::RTD):
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return validated<op, validate>(AddressingMode::ImmediateData);
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//
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// MARK: Impossible error case.
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//
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@ -898,6 +955,7 @@ template <uint8_t op, bool validate> Preinstruction Predecoder<model>::decode(ui
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// MARK: - Page decoders.
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#define Decode(y) return decode<OpT(y)>(instruction)
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#define DecodeReq(x, y) if constexpr (x) Decode(y); break;
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template <Model model>
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Preinstruction Predecoder<model>::decode0(uint16_t instruction) {
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@ -957,6 +1015,8 @@ Preinstruction Predecoder<model>::decode0(uint16_t instruction) {
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case 0xc40: Decode(CMPIw);
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case 0xc80: Decode(CMPIl);
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case 0x6c0: DecodeReq(model == Model::M68020, Op::CALLM); // 4-64 (p168)
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default: break;
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}
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@ -1023,6 +1083,7 @@ Preinstruction Predecoder<model>::decode4(uint16_t instruction) {
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case 0xe71: Decode(Op::NOP); // 4-147 (p251)
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case 0xe72: Decode(Op::STOP); // 6-85 (p539)
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case 0xe73: Decode(Op::RTE); // 6-84 (p538)
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case 0xe74: DecodeReq(model >= Model::M68010, Op::RTD); // 4-166 (p270)
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case 0xe75: Decode(Op::RTS); // 4-169 (p273)
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case 0xe76: Decode(Op::TRAPV); // 4-191 (p295)
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case 0xe77: Decode(Op::RTR); // 4-168 (p272)
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@ -1031,6 +1092,7 @@ Preinstruction Predecoder<model>::decode4(uint16_t instruction) {
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switch(instruction & 0xff8) {
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case 0x840: Decode(Op::SWAP); // 4-185 (p289)
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case 0x848: DecodeReq(model >= Model::M68010, Op::BKPT); // 4-54 (p158)
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case 0x880: Decode(Op::EXTbtow); // 4-106 (p210)
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case 0x8c0: Decode(Op::EXTwtol); // 4-106 (p210)
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case 0xe50: Decode(Op::LINKw); // 4-111 (p215)
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@ -1399,6 +1461,15 @@ Preinstruction Predecoder<model>::decodeE(uint16_t instruction) {
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case 0x6c0: Decode(Op::RORm); // 4-160 (p264)
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case 0x7c0: Decode(Op::ROLm); // 4-160 (p264)
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case 0x8c0: DecodeReq(model >= Model::M68020, Op::BFTST); // 4-51 (p155)
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case 0x9c0: DecodeReq(model >= Model::M68020, Op::BFFFO); // 4-43 (p147)
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case 0xac0: DecodeReq(model >= Model::M68020, Op::BFCHG); // 4-33 (p137)
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case 0xbc0: DecodeReq(model >= Model::M68020, Op::BFEXTS); // 4-37 (p141)
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case 0xcc0: DecodeReq(model >= Model::M68020, Op::BFCLR); // 4-35 (p139)
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case 0xdc0: DecodeReq(model >= Model::M68020, Op::BFEXTU); // 4-40 (p144) [though the given opcode is wrong]
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case 0xec0: DecodeReq(model >= Model::M68020, Op::BFSET); // 4-49 (p153)
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case 0xfc0: DecodeReq(model >= Model::M68020, Op::BFINS); // 4-46 (p150)
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default: break;
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}
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@ -1455,6 +1526,7 @@ Preinstruction Predecoder<model>::decodeF(uint16_t) {
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}
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#undef Decode
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#undef DecodeRef
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// MARK: - Main decoder.
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@ -112,6 +112,10 @@ constexpr DataSize operand_size(Operation r_operation) {
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case Operation::EXTwtol:
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case Operation::UNLINK:
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return DataSize::LongWord;
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default:
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// 68020 TODO.
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return DataSize::Byte;
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}
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}
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@ -21,6 +21,10 @@ namespace M68k {
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enum class Operation: uint8_t {
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Undefined,
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//
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// 68000 operations.
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//
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NOP,
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ABCD, SBCD, NBCD,
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@ -101,7 +105,38 @@ enum class Operation: uint8_t {
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STOP, RESET,
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Max = RESET
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//
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// 68020 additions.
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//
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BKPT,
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BFCHG, BFCLR,
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BFEXTS, BFEXTU,
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BFFFO, BFINS,
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BFSET, BFTST,
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CALLM, RTD, RTM,
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CAS, CAS2,
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CHK2, CMP2,
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DIVSL,
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EXTbtol,
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PACK, UNPK,
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TRAPcc,
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cpBcc, cpDBcc, cpGEN,
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cpScc, cpTRAPcc, cpRESTORE,
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cpSAVE,
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MOVEfromCCR,
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MOVEC, MOVES,
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//
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// Introspection.
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//
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Max = MOVES
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};
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const char *to_string(Operation op);
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@ -147,6 +182,7 @@ constexpr uint32_t quick(uint16_t instruction, Operation r_op = Operation::Undef
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case Operation::BSRb:
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case Operation::MOVEl: return uint32_t(int8_t(instruction));
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case Operation::TRAP: return uint32_t(instruction & 15);
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case Operation::BKPT: return uint32_t(instruction & 7);
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default: {
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uint32_t value = (instruction >> 9) & 7;
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value |= (value - 1)&8;
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