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mirror of https://github.com/TomHarte/CLK.git synced 2024-11-22 12:33:29 +00:00

Switch meaning of bit 2.

This commit is contained in:
Thomas Harte 2024-02-15 08:54:52 -05:00
parent 809bc9d6a8
commit cb22278c7f
3 changed files with 18 additions and 4 deletions

View File

@ -376,6 +376,17 @@ void AY38910SampleSource<is_stereo>::set_control_lines(ControlLines control_line
update_bus(); update_bus();
} }
template <bool is_stereo>
void AY38910SampleSource<is_stereo>::set_reset(bool active) {
if(active == reset_) return;
reset_ = active;
// Reset upon the leading edge; TODO: is this right?
if(reset_) {
reset();
}
}
template <bool is_stereo> template <bool is_stereo>
void AY38910SampleSource<is_stereo>::reset() { void AY38910SampleSource<is_stereo>::reset() {
// TODO: the below is a guess. Look up real answers. // TODO: the below is a guess. Look up real answers.

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@ -84,6 +84,9 @@ template <bool stereo> class AY38910SampleSource {
/// Strobes the reset line. /// Strobes the reset line.
void reset(); void reset();
/// Sets the current value of the reset line.
void set_reset(bool reset);
/*! /*!
Gets the value that would appear on the requested interface port if it were in output mode. Gets the value that would appear on the requested interface port if it were in output mode.
@parameter port_b @c true to get the value for Port B, @c false to get the value for Port A. @parameter port_b @c true to get the value for Port B, @c false to get the value for Port A.
@ -118,6 +121,8 @@ template <bool stereo> class AY38910SampleSource {
private: private:
Concurrency::AsyncTaskQueue<false> &task_queue_; Concurrency::AsyncTaskQueue<false> &task_queue_;
bool reset_ = false;
int selected_register_ = 0; int selected_register_ = 0;
uint8_t registers_[16]{}; uint8_t registers_[16]{};
uint8_t output_registers_[16]{}; uint8_t output_registers_[16]{};

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@ -103,13 +103,11 @@ class Mockingboard: public Card {
ControlLines( ControlLines(
((value & 1) ? ControlLines::BC1 : 0) | ((value & 1) ? ControlLines::BC1 : 0) |
((value & 2) ? ControlLines::BDIR : 0) | ((value & 2) ? ControlLines::BDIR : 0) |
((value & 4) ? ControlLines::BC2 : 0) ControlLines::BC2
) )
); );
if(!value) { ay.set_reset(!(value & 4));
ay.reset();
}
} else { } else {
ay.set_data_input(value); ay.set_data_input(value);
} }